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// Initialize and wait for CLA1ToCPUMsgRAM
//
MemCfgRegs.MSGxINIT.bit.INIT_CLA1TOCPU = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CLA1TOCPU != 1){};
//
// Initialize and wait for CPUToCLA1MsgRAM
//
MemCfgRegs.MSGxINIT.bit.INIT_CPUTOCLA1 = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CPUTOCLA1 != 1){};
//
// Select LS5RAM to be the programming space for the CLA
// First configure the CLA to be the master for LS5 and then
// set the space to be a program block
//
MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 1;
//
// Next configure LS0RAM and LS1RAM as data spaces for the CLA
// First configure the CLA to be the master for LS0(1) and then
// set the spaces to be code blocks
//
MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 0;
//
// Compute all CLA task vectors
// On Type-1 CLAs the MVECT registers accept full 16-bit task addresses as
// opposed to offsets used on older Type-0 CLAs
//
EALLOW;
#pragma diag_suppress 770
Cla1Regs.MVECT1 = (Uint16)(&Cla1Task1);
Cla1Regs.MVECT2 = (Uint16)(&Cla1Task2);
Cla1Regs.MVECT3 = (Uint16)(&Cla1Task3);
Cla1Regs.MVECT4 = (Uint16)(&Cla1Task4);
Cla1Regs.MVECT5 = (Uint16)(&Cla1Task5);
Cla1Regs.MVECT6 = (Uint16)(&Cla1Task6);
Cla1Regs.MVECT7 = (Uint16)(&Cla1Task7);
Cla1Regs.MVECT8 = (Uint16)(&Cla1Task8);
#pragma diag_default 770
// //
// // Enable the IACK instruction to start a task on CLA in software
// // for all 8 CLA tasks. Also, globally enable all 8 tasks (or a
// // subset of tasks) by writing to their respective bits in the
// // MIER register
// //
// Cla1Regs.MCTL.bit.IACKE = 1;
// Cla1Regs.MIER.all = 0x00FF;
DmaClaSrcSelRegs.CLA1TASKSRCSEL1.bit.TASK1 = 36; //EPWM12 INT trigger CLA task1
Cla1Regs.MIER.all = M_INT1; //使能任务1
EDIS;
//
// Configure the vectors for the end-of-task interrupt for all
// 8 tasks
//
PieVectTable.CLA1_1_INT = &cla1Isr1;
PieVectTable.CLA1_2_INT = &cla1Isr2;
PieVectTable.CLA1_3_INT = &cla1Isr3;
PieVectTable.CLA1_4_INT = &cla1Isr4;
PieVectTable.CLA1_5_INT = &cla1Isr5;
PieVectTable.CLA1_6_INT = &cla1Isr6;
PieVectTable.CLA1_7_INT = &cla1Isr7;
PieVectTable.CLA1_8_INT = &cla1Isr8;
//
// Enable CLA interrupts at the group and subgroup levels
//
//PieCtrlRegs.PIEIER11.all = 0xFFFF;
//IER |= (M_INT11 );
// Disable CLA interrupts at the group and subgroup levels
//
PieCtrlRegs.PIEIER11.all = 0x0000;
IER = 0x0000;
EPWM中断源配置
//EPWM1A --> INT & ADC Trigger //
EALLOW;
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_HI; // Forced Hi (EPWM1A = High state)
EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_HI; // Forced Hi (EPWM1B = High state)
EPwm1Regs.TZFRC.bit.OST = 1; // Forces a fault on the OST latch and sets the OSTFLG bit.
EDIS;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE; // This will clear CMPA Register
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE; // This will clear CMPB Register
EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period
EPwm1Regs.CMPA.bit.CMPA = 600 + EPWM1_CMPA_INT_CNT; // CMPRA=1us
EPwm1Regs.CMPB.bit.CMPB = 600;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP; // Count up when synchronization
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL=TB_CTR_ZERO;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.AQCTLA.bit.CAU = AQ_NO_ACTION; // CNT = CMP up ->1
EPwm1Regs.AQCTLA.bit.CAD = AQ_NO_ACTION; // CNT = CMP down ->no action
EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // CNT = 0, -->0, Start the Logic ADC when counter reach zero
EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST; // One event will generate a SCOA pulse
// EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO; // SOCA PULSE GENERAT A TB=0
EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTRU_CMPB;
// EPwm1Regs.ETSEL.bit.SOCASELCMP = 0; // SOCA Plues Generate By CompareA
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // ENABLE SOCA PULSE
// EPwm1Regs.ETCNTINITCTL.bit.SOCAINITEN = 0;
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTRU_CMPA; // INT when TB count up and TB=cmpra
EPwm1Regs.ETSEL.bit.INTEN = 0; // Disable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1rd event
EPwm1Regs.AQCTL.bit.SHDWAQAMODE = 1;
EPwm1Regs.AQCTL.bit.LDAQAMODE = 1;
EPwm1Regs.AQSFRC.bit.RLDCSF = 0; // the active register load on event counter equal to zero
EPwm1Regs.AQCSFRC.bit.CSFA = FORCE_HIGH; // Software forcing disabled, i.e., has no effect
EPwm1Regs.AQCSFRC.bit.CSFB = AQC_NO_ACTION;
//EPWM2A --> INT2 Trigger //
EALLOW;
EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_HI; // Forced Hi (EPWM1A = High state)
EPwm2Regs.TZFRC.bit.OST = 1; // Forces a fault on the OST latch and sets the OSTFLG bit.
EDIS;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE; // This will clear CMPA Register
EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Set timer period
EPwm2Regs.CMPA.bit.CMPA = 600 + EPWM1_CMPA_INT_CNT; // CMPRA=1us
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP; // Count up when synchronization
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL=TB_CTR_ZERO;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.AQCTLA.bit.CAU = AQ_NO_ACTION; // CNT = CMP up ->1
EPwm2Regs.AQCTLA.bit.CAD = AQ_NO_ACTION; // CNT = CMP down ->no action
EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // CNT = 0, -->0, Start the Logic ADC when counter reach zero
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTRU_CMPA; // INT when TB count up and TB=cmpra
EPwm2Regs.ETSEL.bit.INTEN = 0; // Disable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1rd event
EPwm2Regs.AQCTL.bit.SHDWAQAMODE = 1;
EPwm2Regs.AQCTL.bit.LDAQAMODE = 1;
EPwm2Regs.AQSFRC.bit.RLDCSF = 0; // the active register load on event counter equal to zero
EPwm2Regs.AQCSFRC.bit.CSFA = FORCE_HIGH;
