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反正我是没有找到,自己写吧,把例程中的dma_ram_to_ram的参数稍微改一下,搬到workshop的lab4-1,稍微修改就差不多了。碰巧我前两天也在做这一块。
//###########################################################################
//real sampling and real firlting;
//###########################################################################
//
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
#include <string.h>
#include "FPU.h"
#include "math.h"
#include "float.h"
#include "config.h"
#define C28_FREQ 150 //C28 CPU frequency in MHz
extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadSize;
extern Uint16 RamfuncsRunStart;
extern float Value_num;
void config_ADC1(void);
void main(void)
{
InitSysCtrl(); // Init C28 core
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // GPIO0 = ePWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // GPIO0 = ePWM1B
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // GPIO0 = ePWM2A
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // GPIO0 = ePWM2B
EDIS;
// Copy time critical code and Flash setup code to RAM
// This includes the following functions: InitFlash();
// The RamfuncsLoadStart, RamfuncsLoadSize and RamfuncsRunStart
// symbols are created by the linker. Refer to the device .cmd file.
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
// Call Flash Initialization to setup flash waitstates
// This function must reside in RAM
InitFlash();
Init_firFP();
Value_num=CC_TBPRD/4095.0; // CMPA/B=(fir_A0/2^12)*CC_TBPRD=fir_A0*Value_num
InitAdc1();
config_ADC1();
config_PWM();
DINT;
InitPieCtrl();
IER=0x0000;
IFR=0x0000;
InitPieVectTable();
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.ADCINT1 = &ADCINT1_ISR;
EDIS;
InitCpuTimers();
ConfigCpuTimer(&CpuTimer0, C28_FREQ, 100); //AD采样间隔 100us
//Enable INT
PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
IER |= M_INT1;
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
CpuTimer0Regs.TCR.bit.TSS = 0; // start T0
while(1) ;
}
void config_ADC1(void)
{
InitAdc1();
EALLOW;
Adc1Regs.ADCCTL2.bit.ADCNONOVERLAP = 1; // Enable non-overlap mode i.e. Overlap of sample is not allowed
Adc1Regs.ADCCTL1.bit.INTPULSEPOS = 1; // ADCINT1 trips after AdcResults latch
Adc1Regs.INTSEL1N2.bit.INT1E = 1; // Enabled ADCINT1
Adc1Regs.INTSEL1N2.bit.INT1CONT = 1; // Disable ADCINT1 Continuous mode
Adc1Regs.INTSEL1N2.bit.INT1SEL = 3; // setup EOC0 to trigger ADCINT1 to fire
AnalogSysctrlRegs.TRIG1SEL.all = 1; // Assigning TINT0 to ADC-TRIGGER 1
AnalogSysctrlRegs.CCLKCTL.all =ACLKDIV4; //ASYSCLK=PLLCLK/ACLKDIV
Adc1Regs.ADCSOC0CTL.bit.CHSEL = 0; // set SOC0 channel select to ADC1in_A0
Adc1Regs.ADCSOC0CTL.bit.TRIGSEL = 5; // Set SOC0 start trigger1
Adc1Regs.ADCSOC0CTL.bit.ACQPS = 6; // set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS + 1)
Adc1Regs.ADCSOC1CTL.bit.CHSEL = 8; // set SOC1 channel select to ADC1in_A0
Adc1Regs.ADCSOC1CTL.bit.TRIGSEL = 5; // Set SOC1 start trigger1
Adc1Regs.ADCSOC1CTL.bit.ACQPS = 6; // set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS + 1)
Adc1Regs.ADCSOC2CTL.bit.CHSEL = 2; // set SOC2 channel select to ADC1in_A0
Adc1Regs.ADCSOC2CTL.bit.TRIGSEL = 5; // Set SOC2 start trigger1
Adc1Regs.ADCSOC2CTL.bit.ACQPS = 6; // set SOC2 S/H Window to 7 ADC Clock Cycles, (6 ACQPS + 1)
Adc1Regs.ADCSOC3CTL.bit.CHSEL = 3; // set SOC3 channel select to ADC1in_A0
Adc1Regs.ADCSOC3CTL.bit.TRIGSEL = 5; // Set SOC3 start trigger1
Adc1Regs.ADCSOC3CTL.bit.ACQPS = 6; // set SOC3 S/H Window to 7 ADC Clock Cycles, (6 ACQPS + 1)
EDIS;
}
Init_firFP();
Value_num=CC_TBPRD/4095.0; // CMPA/B=(fir_A0/2^12)*CC_TBPRD=fir_A0*Value_num
这两行也要去了,不需要用。
qiuhong yao 说://###########################################################################
//real sampling and real firlting;
//###########################################################################
//#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
#include <string.h>
#include "FPU.h"
#include "math.h"
#include "float.h"
#include "config.h"
#define C28_FREQ 150 //C28 CPU frequency in MHzextern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadSize;
extern Uint16 RamfuncsRunStart;extern float Value_num;
void config_ADC1(void);void main(void)
{
InitSysCtrl(); // Init C28 core
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // GPIO0 = ePWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // GPIO0 = ePWM1B
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // GPIO0 = ePWM2A
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // GPIO0 = ePWM2B
EDIS;// Copy time critical code and Flash setup code to RAM
// This includes the following functions: InitFlash();
// The RamfuncsLoadStart, RamfuncsLoadSize and RamfuncsRunStart
// symbols are created by the linker. Refer to the device .cmd file.
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
// Call Flash Initialization to setup flash waitstates
// This function must reside in RAM
InitFlash();Init_firFP();
Value_num=CC_TBPRD/4095.0; // CMPA/B=(fir_A0/2^12)*CC_TBPRD=fir_A0*Value_numInitAdc1();
config_ADC1();config_PWM();
DINT;
InitPieCtrl();
IER=0x0000;
IFR=0x0000;
InitPieVectTable();
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.ADCINT1 = &ADCINT1_ISR;
EDIS;
InitCpuTimers();
ConfigCpuTimer(&CpuTimer0, C28_FREQ, 100); //AD采样间隔 100us
//Enable INT
PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
IER |= M_INT1;
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGMCpuTimer0Regs.TCR.bit.TSS = 0; // start T0
while(1) ;
}void config_ADC1(void)
{InitAdc1();
EALLOW;
Adc1Regs.ADCCTL2.bit.ADCNONOVERLAP = 1; // Enable non-overlap mode i.e. Overlap of sample is not allowedAdc1Regs.ADCCTL1.bit.INTPULSEPOS = 1; // ADCINT1 trips after AdcResults latch
Adc1Regs.INTSEL1N2.bit.INT1E = 1; // Enabled ADCINT1
Adc1Regs.INTSEL1N2.bit.INT1CONT = 1; // Disable ADCINT1 Continuous mode
Adc1Regs.INTSEL1N2.bit.INT1SEL = 3; // setup EOC0 to trigger ADCINT1 to fireAnalogSysctrlRegs.TRIG1SEL.all = 1; // Assigning TINT0 to ADC-TRIGGER 1
AnalogSysctrlRegs.CCLKCTL.all =ACLKDIV4; //ASYSCLK=PLLCLK/ACLKDIVAdc1Regs.ADCSOC0CTL.bit.CHSEL = 0; // set SOC0 channel select to ADC1in_A0
Adc1Regs.ADCSOC0CTL.bit.TRIGSEL = 5; // Set SOC0 start trigger1
Adc1Regs.ADCSOC0CTL.bit.ACQPS = 6; // set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS + 1)Adc1Regs.ADCSOC1CTL.bit.CHSEL = 8; // set SOC1 channel select to ADC1in_A0
Adc1Regs.ADCSOC1CTL.bit.TRIGSEL = 5; // Set SOC1 start trigger1
Adc1Regs.ADCSOC1CTL.bit.ACQPS = 6; // set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS + 1)Adc1Regs.ADCSOC2CTL.bit.CHSEL = 2; // set SOC2 channel select to ADC1in_A0
Adc1Regs.ADCSOC2CTL.bit.TRIGSEL = 5; // Set SOC2 start trigger1
Adc1Regs.ADCSOC2CTL.bit.ACQPS = 6; // set SOC2 S/H Window to 7 ADC Clock Cycles, (6 ACQPS + 1)Adc1Regs.ADCSOC3CTL.bit.CHSEL = 3; // set SOC3 channel select to ADC1in_A0
Adc1Regs.ADCSOC3CTL.bit.TRIGSEL = 5; // Set SOC3 start trigger1
Adc1Regs.ADCSOC3CTL.bit.ACQPS = 6; // set SOC3 S/H Window to 7 ADC Clock Cycles, (6 ACQPS + 1)EDIS;
}
首先感谢您的积极解答和分享。但我注意到以上代码里没有DMA传输的设置。您的F28M35x ADC结果“使用DMA传输”的程序写出来了吗?可否分享交流一下?
哎呀,失误失误,我当时打开的文件太多了,把一个类似文件的内容拷贝过来了。
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
#include <string.h>
#include "FPU.h"
#include "math.h"
#include "float.h"
#include "config.h"
#define C28_FREQ 150 //C28 CPU frequency in MHz
extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadSize;
extern Uint16 RamfuncsRunStart;
extern float Value_num;
Uint16 Gpio70_count;
#pragma DATA_SECTION(adc_buffer, "DMARAML2")
volatile Uint16 adc_buffer[40];
volatile Uint16 *DMADest;
volatile Uint16 *DMASource;
interrupt void local_DINTCH1_ISR(void);
void config_ADC1(void);
void main(void)
{
InitSysCtrl(); // Init C28 core
EALLOW;
GpioCtrlRegs.GPCMUX1.bit.GPIO70=0;
GpioCtrlRegs.GPCDIR.bit.GPIO70=1;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // GPIO0 = ePWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // GPIO0 = ePWM1B
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // GPIO0 = ePWM2A
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // GPIO0 = ePWM2B
EDIS;
// Copy time critical code and Flash setup code to RAM
// This includes the following functions: InitFlash();
// The RamfuncsLoadStart, RamfuncsLoadSize and RamfuncsRunStart
// symbols are created by the linker. Refer to the device .cmd file.
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
// Call Flash Initialization to setup flash waitstates
// This function must reside in RAM
InitFlash();
// Init_firFP();
// Value_num=CC_TBPRD/4095.0; // CMPA/B=(fir_A0/2^12)*CC_TBPRD=fir_A0*Value_num
config_ADC1();
// config_PWM();
DINT;
InitPieCtrl();
IER=0x0000;
IFR=0x0000;
InitPieVectTable();
EALLOW; // This is needed to write to EALLOW protected registers
// PieVectTable.ADCINT1 = &ADCINT1_ISR;
PieVectTable.DINTCH1 = &local_DINTCH1_ISR;
EDIS;
DMADest=adc_buffer;
DMASource=&Adc1Result.ADCRESULT0;
DMAInitialize();
DMACH1AddrConfig(DMADest,DMASource);
DMACH1BurstConfig(3,1,10);
DMACH1TransferConfig(9,0xfffd,0xffe3);
DMACH1WrapConfig(0xffff,0,0xffff,0);
DMACH1ModeConfig(DMA_ADCINT1,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,
SYNC_DISABLE,SYNC_SRC,OVRFLOW_DISABLE,SIXTEEN_BIT,
CHINT_END,
CHINT_ENABLE);
InitCpuTimers();
ConfigCpuTimer(&CpuTimer0, C28_FREQ, 100); //AD采样间隔 100us
//Enable INT
// PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
IER |= M_INT7;
EnableInterrupts();
// EINT; // Enable Global interrupt INTM
// ERTM; // Enable Global realtime interrupt DBGM
GpioDataRegs.GPCDAT.bit.GPIO70=0;
CpuTimer0Regs.TCR.bit.TSS = 0; // start T0
StartDMACH1();
while(1) ;
}
__interrupt void local_DINTCH1_ISR(void)
{
// if(Gpio70_count++==1000)
// {
GpioDataRegs.GPCDAT.bit.GPIO70^=1;
// Gpio70_count=0;
// }
PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
StartDMACH1();
}
void config_ADC1(void)
{
InitAdc1();
EALLOW;
Adc1Regs.ADCCTL2.bit.ADCNONOVERLAP = 1; // Enable non-overlap mode i.e. Overlap of sample is not allowed
Adc1Regs.ADCCTL1.bit.INTPULSEPOS = 1; // ADCINT1 trips after AdcResults latch
Adc1Regs.INTSEL1N2.bit.INT1E = 1; // Enabled ADCINT1
Adc1Regs.INTSEL1N2.bit.INT1CONT = 1; // Disable ADCINT1 Continuous mode
Adc1Regs.INTSEL1N2.bit.INT1SEL = 3; // setup EOC0 to trigger ADCINT1 to fire
AnalogSysctrlRegs.TRIG1SEL.all = 1; // Assigning TINT0 to ADC-TRIGGER 1
AnalogSysctrlRegs.CCLKCTL.all =ACLKDIV4; //ASYSCLK=PLLCLK/ACLKDIV
Adc1Regs.ADCSOC0CTL.bit.CHSEL = 0; // set SOC0 channel select to ADC1in_A0
Adc1Regs.ADCSOC0CTL.bit.TRIGSEL = 5; // Set SOC0 start trigger1
Adc1Regs.ADCSOC0CTL.bit.ACQPS = 6; // set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS + 1)
Adc1Regs.ADCSOC1CTL.bit.CHSEL = 8; // set SOC1 channel select to ADC1in_A0
Adc1Regs.ADCSOC1CTL.bit.TRIGSEL = 5; // Set SOC1 start trigger1
Adc1Regs.ADCSOC1CTL.bit.ACQPS = 6; // set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS + 1)
Adc1Regs.ADCSOC2CTL.bit.CHSEL = 2; // set SOC2 channel select to ADC1in_A0
Adc1Regs.ADCSOC2CTL.bit.TRIGSEL = 5; // Set SOC2 start trigger1
Adc1Regs.ADCSOC2CTL.bit.ACQPS = 6; // set SOC2 S/H Window to 7 ADC Clock Cycles, (6 ACQPS + 1)
Adc1Regs.ADCSOC3CTL.bit.CHSEL = 3; // set SOC3 channel select to ADC1in_A0
Adc1Regs.ADCSOC3CTL.bit.TRIGSEL = 5; // Set SOC3 start trigger1
Adc1Regs.ADCSOC3CTL.bit.ACQPS = 6; // set SOC3 S/H Window to 7 ADC Clock Cycles, (6 ACQPS + 1)
EDIS;
}