本意是想配置两路PWM信号,其中PWM2与PWM1相位差180,但是按照如图所示的方式配置后,输出结果仍有几十ns的误差,不知是何原因
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void Setup_ePWM1(void)
{
// EALLOW;
// SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
// SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1;
// EDIS;
EPwm1Regs.TBPRD = SP; //
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //
EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; //
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //�
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; //TBCLK = SYSCLKOUT / (HSPCLKDIV �� CLKDIV)=60M
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare
EPwm1Regs.CMPA.half.CMPA = CMP1A; //
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on CAU��TBCTR=CMPA
EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Clear PWM1A on CAD,TBCTR=CMPA
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM1B on CAU��TBCTR=CMPA
EPwm1Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM1B on CAD,TBCTR=CMPA
// Active Low PWMs - Setup Deadband
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;//
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; //
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;//A
EPwm1Regs.DBRED = DT; //
EPwm1Regs.DBFED = DT;
// Assumes ePWM1 clock is already enabled in InitSysCtrl();
//
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // TBCTR = 0
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
}
void Setup_ePWM2(void)
{
// EALLOW;
// SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
// SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1;
// EDIS;
EPwm2Regs.TBPRD = SP; //
EPwm2Regs.TBPHS.half.TBPHS = SP/2; // Phase is 0
// EPwm2Regs.TBPHS.half.TBPHS = 0; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; //
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Setup compare
EPwm2Regs.CMPA.half.CMPA = CMP1A; //
// Set action
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on CAU
EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Clear PWM2A on CAD
EPwm2Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM2B on CAU
EPwm2Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM2B on CAD
// Active Low complementary PWMs - setup the deadband
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;//
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; //
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;//
EPwm2Regs.DBRED = DT; //
EPwm2Regs.DBFED = DT;
//
// EALLOW;
// SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Start all the timers synced
// EDIS;
}