TMS320F28035: 峰值电流控制HVPSFB例程的一些疑问

void PWMDRV_PSFB_PCMC_CNF(int16 n, int16 period, int16 SR_Enable, int16 Comp2_Prot)
{
// n = the ePWM module number, i.e. selects the target module for init.
// ePWM(n) init.  Note EPWM(n) is the Master
	
	//Time Base SubModule Register
	(*ePWM[n]).TBCTL.bit.PRDLD = TB_IMMEDIATE;			// Set Immediate load
	(*ePWM[n]).TBPRD = period;
	(*ePWM[n]).TBPHS.half.TBPHS = 0;
	(*ePWM[n]).TBCTR = 0;

	(*ePWM[n]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
	(*ePWM[n]).TBCTL.bit.PHSEN = TB_DISABLE;
	(*ePWM[n]).TBCTL.bit.SYNCOSEL = TB_CTR_CMPB; 		// Used to sync EPWM(n+1) "down-stream"
	(*ePWM[n]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
	(*ePWM[n]).TBCTL.bit.CLKDIV = TB_DIV1;

	// Counter compare submodule registers
	(*ePWM[n]).CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
	(*ePWM[n]).CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE; 	
	(*ePWM[n]).CMPA.half.CMPA = period-68;				
	(*ePWM[n]).CMPB = period;

	// Action Qualifier SubModule Registers
	(*ePWM[n]).AQCTLA.bit.ZRO = AQ_SET;
	(*ePWM[n]).AQCTLA.bit.PRD = AQ_CLEAR;
	
	// DeadBand Control Register
	(*ePWM[n]).DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
	(*ePWM[n]).DBCTL.bit.POLSEL = DB_ACTV_HIC;			// Active Hi Complimentary
	(*ePWM[n]).DBRED = 20;								// Initial value
	(*ePWM[n]).DBFED = 20;								// Initial value

// ePWM(n+1) init.  EPWM(n+1) is a slave

	//Time Base SubModule Register
	(*ePWM[n+1]).TBCTL.bit.PRDLD = TB_SHADOW;
	(*ePWM[n+1]).TBPRD = period-1;
	(*ePWM[n+1]).TBPHS.half.TBPHS = 0; 					
	(*ePWM[n+1]).TBCTR = 0;

	(*ePWM[n+1]).TBCTL.bit.CTRMODE = TB_COUNT_UP;
	(*ePWM[n+1]).TBCTL.bit.PHSEN = TB_ENABLE;
	(*ePWM[n+1]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN; 		// Sync "flow through" mode
	(*ePWM[n+1]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
	(*ePWM[n+1]).TBCTL.bit.CLKDIV = TB_DIV1;

	// Counter compare submodule registers
	(*ePWM[n+1]).CMPA.half.CMPA = period + 10;			// Initial value 
	(*ePWM[n+1]).CMPB = 20; 							// Initial value 
	(*ePWM[n+1]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
	(*ePWM[n+1]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
	(*ePWM[n+1]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
	(*ePWM[n+1]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;
	
	// Action Qualifier SubModule Registers
	(*ePWM[n+1]).AQCTLA.bit.CAU = AQ_SET;
	(*ePWM[n+1]).AQCTLA.bit.CBU = AQ_CLEAR;
	(*ePWM[n+1]).AQCTLA.bit.ZRO = AQ_CLEAR;
	(*ePWM[n+1]).AQCTLA.bit.PRD = AQ_CLEAR;	

	(*ePWM[n+1]).AQCTLB.bit.CBU = AQ_SET; 
	(*ePWM[n+1]).AQCTLB.bit.CAU = AQ_CLEAR; 
	(*ePWM[n+1]).AQCTLB.bit.ZRO = AQ_CLEAR; 
	(*ePWM[n+1]).AQCTLB.bit.PRD = AQ_CLEAR; 


// Cycle-by-cycle shutdown mechanism configuration

	EALLOW;	
//===========================================================================
// Define an event (DCAEVT1) based on Comparator 1 Output
	(*ePWM[n+1]).DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT; 	// DCAH = Comparator 1 output
	(*ePWM[n+1]).TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI; 			// DCAEVT1 = DCAH high(will become active
															// as Comparator output goes high)
	(*ePWM[n+1]).DCACTL.bit.EVT1SRCSEL = DC_EVT_FLT; 		// DCAEVT1 = DC_EVT_FLT (filtered)
	(*ePWM[n+1]).DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC;	// Take async path

// Enable DCAEVT1 as a one-shot source
	(*ePWM[n+1]).TZSEL.bit.DCAEVT1 = 1;						// Enable One-Shot Trip

// Following code for the sync mechanism based on the same trigger event - COMPxOUT
	(*ePWM[n+1]).DCACTL.bit.EVT1SYNCE = 1;					// Sync enabled

// What do we want the DCAEVT1 event to do? - Initial Configuration
	(*ePWM[n+1]).TZCTL.bit.TZA = TZ_NO_CHANGE; 				// EPWMxA - no change 
	(*ePWM[n+1]).TZCTL.bit.TZB = TZ_FORCE_LO; 				// EPWMxB - go low 

//===========================================================================
// Event Filtering Configuration
	(*ePWM[n+1]).DCFCTL.bit.SRCSEL = DC_SRC_DCAEVT1;
	(*ePWM[n+1]).DCFCTL.bit.BLANKE = DC_BLANK_ENABLE; 
	(*ePWM[n+1]).DCFCTL.bit.PULSESEL = DC_PULSESEL_ZERO;

	(*ePWM[n+1]).DCFOFFSET = 2; 					 		// Blanking Window Offset = CMPA(n+1)
	(*ePWM[n+1]).DCFWINDOW = 4; 							// Blanking window length - initial value
//===========================================================================
	EDIS;

在上述的配置epwm1模块以及epwm2模块的代码中，有一些我不太理解的地方：

1.首先是epwm1模块将计数到CMPB时记为一次同步信号输出，同步信号输出到epwm2中，而epwm2模块的DCAEVT1事件的配置中，同样使能了DCAEVT1的同步信号，那epwm2模块会响应两个同步信号吗，如果是响应两个同步信号，峰值电流控制的波形就不太对了。

2.其次是在设置epwm2时，将PRD设置为period-1，而CMPA设置为period+10，那下方AQ配置中的CAU事件又是怎么触发的。

3.整段函数读下来我无法和峰值电流控制的波形所对应，由于我还没有完整地分析过此例程，此例程还配合其他部分来产生峰值电流控制的epwm了吗？