TMS320F28388D: 无法在cpu1的epwm中断里面，嵌套cpu1的ipc中断（CMTOCPUx IPCINTR0）

DH Z

Prodigy 10 points

Part Number: TMS320F28388D

参照例程1、interrupt\interrupt_ex3_sw_prioritization.c

2、ipc_ex1_basic_c28x1.c

3、ipc_ex1_basic_cm.c

无法在epwm中断里面，嵌套来自M4触发的ipc中断

2 年多前

0 DH Z 2 年多前

Prodigy 10 points

EPWM的中断嵌套设置：

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__interrupt void epwm1ISR(void)
{
    //
    // Save IER register on stack
    //
    volatile uint16_t tempPIEIER = HWREGH(PIECTRL_BASE + PIE_O_IER3);
    
    //
    // Set the global and group priority to allow CPU interrupts
    // with higher priority
    IER |= M_INT3;
    IER &= MINT3;
    HWREGH(PIECTRL_BASE + PIE_O_IER3) &= MG3_1;
    
    //
    // Clear INT flag for this timer
    //
    EPWM_clearEventTriggerInterruptFlag(EPWM1_BASE);
    
    //
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__interrupt void epwm1ISR(void)
{
    //
    // Save IER register on stack
    //
    volatile uint16_t tempPIEIER = HWREGH(PIECTRL_BASE + PIE_O_IER3);
    
    //
    // Set the global and group priority to allow CPU interrupts
    // with higher priority

    IER |= M_INT3;
    IER &= MINT3;
    HWREGH(PIECTRL_BASE + PIE_O_IER3) &= MG3_1;
    
    //
    // Clear INT flag for this timer
    //
    EPWM_clearEventTriggerInterruptFlag(EPWM1_BASE);
    
    //
    // Enable Interrupts
    //
    Interrupt_clearACKGroup(0xFFFFU);
    __asm("  NOP");
    EINT;
    
    // Insert ISR Code here.......
    epwm_ISR();
    
    //
    // Disable interrupts and restore registers saved:
    //
    DINT;
    HWREGH(PIECTRL_BASE + PIE_O_IER3) = tempPIEIER;

    //Add ISR to Trace
    traceISR[traceISRIndex % TRACE_SIZE] = 0x0017;
    traceISRIndex++;
    
}

0 DH Z 2 年多前

Prodigy 10 points

中断嵌套的宏定义：

全局：

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#define INT1PL      0       // Global Priority for Group1 Interrupts
#define INT2PL      0        // Global Priority for Group2 Interrupts
#define INT3PL      16        // Global Priority for Group3
#define INT4PL      0        // Global Priority for Group4 Interrupts
#define INT5PL      0        // Global Priority for Group5 Interrupts
#define INT6PL      0        // Global Priority for Group6
#define INT7PL      0        // Global Priority for Group7 Interrupts
#define INT8PL      0        // Global Priority for Group8 Interrupts
#define INT9PL      0        // Global Priority for Group9
#define INT10PL     0        // Global Priority for Group10 Interrupts
#define INT11PL     1        // Global Priority for Group11 Interrupts
#define INT12PL     0        // Global Priority for Grou
#define INT13PL     0        // Global Priority for INT13 (TINT1)
#define INT14PL     0        // Global Priority for INT14 (TINT2)
#define INT15PL     0        // Global Priority for DATALOG
#define INT16PL     0        // Global Priority for RTOSINT
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#define INT1PL      0       // Global Priority for Group1 Interrupts
#define INT2PL      0        // Global Priority for Group2 Interrupts
#define INT3PL      16        // Global Priority for Group3
#define INT4PL      0        // Global Priority for Group4 Interrupts
#define INT5PL      0        // Global Priority for Group5 Interrupts
#define INT6PL      0        // Global Priority for Group6
#define INT7PL      0        // Global Priority for Group7 Interrupts
#define INT8PL      0        // Global Priority for Group8 Interrupts
#define INT9PL      0        // Global Priority for Group9
#define INT10PL     0        // Global Priority for Group10 Interrupts
#define INT11PL     1        // Global Priority for Group11 Interrupts
#define INT12PL     0        // Global Priority for Grou
#define INT13PL     0        // Global Priority for INT13 (TINT1)
#define INT14PL     0        // Global Priority for INT14 (TINT2)
#define INT15PL     0        // Global Priority for DATALOG
#define INT16PL     0        // Global Priority for RTOSINT

组：

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#define G3_1PL      1       // EPWM1_INT
#define G3_2PL      0       // EPWM2_INT
#define G3_3PL      0       // EPWM3_INT
#define G3_4PL      0       // EPWM4_INT
#define G3_5PL      0       // EPWM5_INT
#define G3_6PL      0       // EPWM6_INT
#define G3_7PL      0       // EPWM7_INT
#define G3_8PL      0       // EPWM8_INT
#define G3_9PL      0       // EPWM9_INT
#define G3_10PL     0       // EPWM10_INT
#define G3_11PL     0       // EPWM11_INT
#define G3_12PL     0       // EPWM12_INT
#define G3_13PL     0       // EPWM13_INT
#define G3_14PL     0       // EPWM14_INT
#define G3_15PL     0       // EPWM15_INT
#define G3_16PL     0       // EPWM16_INT
#define G11_1PL     0       // CLA1_1_INT
#define G11_2PL     0       // CLA1_2_INT
#define G11_3PL     0       // CLA1_3_INT
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#define G3_1PL      1       // EPWM1_INT
#define G3_2PL      0       // EPWM2_INT
#define G3_3PL      0       // EPWM3_INT
#define G3_4PL      0       // EPWM4_INT
#define G3_5PL      0       // EPWM5_INT
#define G3_6PL      0       // EPWM6_INT
#define G3_7PL      0       // EPWM7_INT
#define G3_8PL      0       // EPWM8_INT
#define G3_9PL      0       // EPWM9_INT
#define G3_10PL     0       // EPWM10_INT
#define G3_11PL     0       // EPWM11_INT
#define G3_12PL     0       // EPWM12_INT
#define G3_13PL     0       // EPWM13_INT
#define G3_14PL     0       // EPWM14_INT
#define G3_15PL     0       // EPWM15_INT
#define G3_16PL     0       // EPWM16_INT


#define G11_1PL     0       // CLA1_1_INT
#define G11_2PL     0       // CLA1_2_INT
#define G11_3PL     0       // CLA1_3_INT
#define G11_4PL     0       // CLA1_4_INT
#define G11_5PL     0       // CLA1_5_INT
#define G11_6PL     0       // CLA1_6_INT
#define G11_7PL     0       // CLA1_7_INT
#define G11_8PL     0       // CLA1_8_INT
#define G11_9PL     1       // CMTOCPUXIPC0_INT
#define G11_10PL    0       // CMTOCPUXIPC1_INT
#define G11_11PL    0       // CMTOCPUXIPC2_INT
#define G11_12PL    0       // CMTOCPUXIPC3_INT
#define G11_13PL    0       // CMTOCPUXIPC4_INT
#define G11_14PL    0       // CMTOCPUXIPC5_INT
#define G11_15PL    0       // CMTOCPUXIPC6_INT
#define G11_16PL    0       // CMTOCPUXIPC7_INT