TMS320F28377D: 新手求助：核2采用spi dma通信 loopback模式，一直未调试成功。但是代发放到核1是可行性（spi_loopback_dma_cpu01），麻烦看一下具体是哪个环节设置错误。

neil lan

Prodigy 90 points

Part Number: TMS320F28377D
Other Parts Discussed in Thread: C2000WARE

1.初始化部分：

#pragma DATA_SECTION(sdata, "REALDATARAM0"); // map the TX data to memory
Uint16 sdata[128]; // Send data buffer

#pragma DATA_SECTION(rdata, "REALDATARAM0"); // map the RX data to memory
Uint16 rdata[128]; // Receive data buffer

REALDATARAM0 在cmd中：

REALDATARAM0 : > RAMM0, PAGE = 0
REALDATARAM1 : > RAMLS1, PAGE = 0

SHARERAMGS0 : > RAMGS0, PAGE = 1
SHARERAMGS1 : > RAMGS1, PAGE = 1
SHARERAMGS2 : > RAMGS2, PAGE = 1

page 0 如下：

RAMM0 : origin = 0x0000A2, length = 0x00035E
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS15 : origin = 0x01B000, length = 0x000FF8

2.初始化SPI

核1

void InitPublicPerip(void)
{
EALLOW;
#ifdef CPU1

//-------------------------------------------
//外设分配
GpioCtrlRegs.GPACSEL4.bit.GPIO31 = 1; // GPIO31 由CLA驱动；00 CPU1 01 cpu1.cla 10 CPU2 11 cpu2.cla
GpioCtrlRegs.GPBCSEL1.bit.GPIO34 = 2; // GPIO34 由CLA驱动；00 CPU1 01 cpu1.cla 10 CPU2 11 cpu2.cla

//
//Enable CPU1.CLA1
//
//DevCfgRegs.DC1.bit.CPU1_CLA1 = 1;

//
//Enable CPU2.CLA1
//
//DevCfgRegs.DC1.bit.CPU2_CLA1 = 1;

//-------------------------------------------
//GSRam分配

//-------------------------------------------
//外设分配
// DevCfgRegs.CPUSEL6.all = 0x08; //SPI to CPU2
DevCfgRegs.CPUSEL6.bit.SPI_A = 1; //SPI to CPU2
DevCfgRegs.CPUSEL6.bit.SPI_B = 1; //SPI to CPU2
DevCfgRegs.CPUSEL6.bit.SPI_C = 1; //SPI to CPU2

DevCfgRegs.CPUSEL8.all = 0x03; //CAN to CPU2

DevCfgRegs.CPUSEL5.bit.SCI_B = 1; //SCI_B to CPU2
DevCfgRegs.CPUSEL5.bit.SCI_A = 1; //SCI_A to CPU2

#endif //CPU1
EDIS;
}

核2

void InitSpi(void)
{
// Initialize SPI-A

// Set reset low before configuration changes
// Clock polarity (0 == rising, 1 == falling)
// 16-bit character
// Enable loop-back

//
// Initialize SPI FIFO registers
//
SpiaRegs.SPIFFRX.all=0x2040; // RX FIFO enabled, clear FIFO int
SpiaRegs.SPIFFRX.bit.RXFFIL = FIFO_LVL; // Set RX FIFO level

SpiaRegs.SPIFFTX.all=0xE040; // FIFOs enabled, TX FIFO released,
SpiaRegs.SPIFFTX.bit.TXFFIL = FIFO_LVL; // Set TX FIFO level

SpiaRegs.SPICCR.bit.SPISWRESET = 0;
SpiaRegs.SPICCR.bit.CLKPOLARITY = 0;
SpiaRegs.SPICCR.bit.SPICHAR = (16-1);

SpiaRegs.SPICCR.bit.SPILBK = 1;

// Enable master (0 == slave, 1 == master)
// Enable transmission (Talk)
// Clock phase (0 == normal, 1 == delayed)
// SPI interrupts are disabled
SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1;
SpiaRegs.SPICTL.bit.TALK = 1;
SpiaRegs.SPICTL.bit.CLK_PHASE = 0;
SpiaRegs.SPICTL.bit.SPIINTENA = 0;

// Set the baud rate
SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = SPI_BRR;

// Set FREE bit
// Halting on a breakpoint will not halt the SPI
SpiaRegs.SPIPRI.bit.FREE = 1;

// Release the SPI from reset
SpiaRegs.SPICCR.bit.SPISWRESET = 1;
}

3.初始化DMA

void dma_init()
{
//
// Initialize DMA
//
DMAInitialize();

DMASource = (volatile Uint16 *)sdata;
DMADest = (volatile Uint16 *)rdata;

//
// configure DMACH5 for TX
//
DMACH5AddrConfig(&SpiaRegs.SPITXBUF,DMASource);
DMACH5BurstConfig(BURST,1,0); // Burst size, src step, dest step
DMACH5TransferConfig(TRANSFER,1,0); // transfer size, src step, dest step
DMACH5ModeConfig(DMA_SPIATX,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,
SYNC_DISABLE,SYNC_SRC,OVRFLOW_DISABLE,SIXTEEN_BIT,
CHINT_END,CHINT_ENABLE);

//
// configure DMA CH6 for RX
//
DMACH6AddrConfig(DMADest,&SpiaRegs.SPIRXBUF);
DMACH6BurstConfig(BURST,0,1);
DMACH6TransferConfig(TRANSFER,0,1);
DMACH6ModeConfig(DMA_SPIARX,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,
SYNC_DISABLE,SYNC_SRC,OVRFLOW_DISABLE,SIXTEEN_BIT,
CHINT_END,CHINT_ENABLE);
}

EALLOW;
CpuSysRegs.SECMSEL.bit.PF2SEL = 1;
EDIS;

4.使能中断

PieVectTable.DMA_CH5_INT= &local_D_INTCH5_ISR;
PieVectTable.DMA_CH6_INT= &local_D_INTCH6_ISR;

PieCtrlRegs.PIEIER7.bit.INTx5 = 1; // Enable PIE Group 7, INT 5 (DMA CH5)
PieCtrlRegs.PIEIER7.bit.INTx6 = 1; // Enable PIE Group 7, INT 6 (DMA CH6)

IER |= M_INT1|M_INT9|M_INT7;

5.使能DMA

StartDMACH6(); // Start SPI RX DMA channel
StartDMACH5(); // Start SPI TX DMA channel

运行完上面代码后发现 rdata中并没有接收到数据。

是不是rdata sdata ram存储的地址问题？还是cpu2使用dma时需cpu1配置？

1 年多前