关于SCI接收中断服务子程序的运行时间问题

请问SCI接收中断子程序是不是不能运行时间太久？我想在里面写一个CAN发送程序，结果发现收到的SCI发过来得数是乱码，请问是什么原因？

unsigned int i=0;

interrupt void scibrxisr(void);

void Scib_init(void);

void Ecana_mbox_init(void);

int a[5];

int DATA=0;

unsigned long po=0;
int o=0;

void main(void)
{
struct ECAN_REGS ECanaShadow;

InitSysCtrl();//设置系统时钟等

InitSciGpio();//设置Sci口，SCIB，18,19

InitECanaGpio();//设置ＣＡＮ通讯口，ECANB,16,17

Scib_init(); // SCI-B设置

InitECana(); //ECANB设置

Ecana_mbox_init();//ECANB邮箱设置


/*以下为中断设置，用到SCI接受中断*/

DINT;

InitPieCtrl();

IER = 0x0000;

IFR = 0x0000;

InitPieVectTable();

EALLOW; // This is needed to write to EALLOW protected registers

PieVectTable.SCIRXINTB = &scibrxisr;

EDIS; // This is needed to disable write to EALLOW protected registers

PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block

PieCtrlRegs.PIEIER9.bit.INTx3=1; // PIE Group 9, INT3

IER|=M_INT9; // Enable CPU INT

EINT;//开全局中断

for(;;);//循环等待

}

interrupt void scibrxisr(void)//中断服务子程序
{
struct ECAN_REGS ECanaShadow;

DATA=ScibRegs.SCIRXBUF.all; // Read data

a[i]=DATA;

ECanaMboxes.MBOX6.MDL.all =a[i];

i++;

ECanaShadow.CANTRS.all = ECanaRegs.CANTRS.all;

ECanaShadow.CANTRS.all = 0;

ECanaShadow.CANTRS.bit.TRS6 = 1; // Set TRS for mailbox under test

ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;

do
{
ECanaShadow.CANTA.all = ECanaRegs.CANTA.all;

} while(ECanaShadow.CANTA.bit.TA6 == 0 ); // Wait for TA5 bit to be set..

ECanaShadow.CANTA.all = 0;

ECanaShadow.CANTA.bit.TA6 = 1; // Clear TA5

ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;

if(i>4) i=0;

po++; // Issue PIE ac

PieCtrlRegs.PIEACK.all|=0x100;

}

void Scib_init()
{
ScibRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
// No parity,8 char bits,
// async mode, idle-line protocol
ScibRegs.SCICTL1.all =0x0001; // enable TX, RX, internal SCICLK,
// Disable RX ERR, SLEEP, TXWAKE
ScibRegs.SCICTL2.bit.RXBKINTENA =1;// ScibRegs.SCICTL2.bit.TXINTENA =1;

ScibRegs.SCIHBAUD =0x00;

ScibRegs.SCILBAUD =0x28;//波特率115200

// ScibRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back
// ScibRegs.SCIFFTX.all=0xC028;
// ScibRegs.SCIFFRX.all=0x2025;
// ScibRegs.SCIFFCT.all=0x00;
ScibRegs.SCICTL1.all =0x0021; // Relinquish SCI from Reset

}

void Ecana_mbox_init()
{

struct ECAN_REGS ECanaShadow;

ECanaMboxes.MBOX6.MSGID.all = 0x80002015; // Extended Identifier

/* Configure Mailbox under test as a Transmit mailbox */

ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;

ECanaShadow.CANMD.bit.MD6 = 0;

ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;

/* Enable Mailbox under test */

ECanaShadow.CANME.all = ECanaRegs.CANME.all;

ECanaShadow.CANME.bit.ME6 = 1;

ECanaRegs.CANME.all = ECanaShadow.CANME.all;

/* Write to DLC field in Master Control reg */

ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 8;

ECanaMboxes.MBOX6.MSGCTRL.bit.RTR = 0;

ECanaMboxes.MBOX6.MSGCTRL.bit.TPL = 0;
}