If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Table 4-25 Secondary Auxiliary Control Register bit functions
为了在FPU中生成未定义的异常，ARM在R4 TRM中给出了一些提示：
section 12.1.1 - "Any data processing instruction that operates on a vector generates an UNDEFINED exception."
section 12.1.2 - "An instruction which attempts to access any of the registers D16-D31 generates an UNDEFINED exception"
section 12.3 - "When a privileged mode is required, an instruction that attempts to access a register in a nonprivileged mode takes the UNDEFINED exception"
section 12.3.3 - "Clearing EN disables VFP functionality, causing all VFP instructions apart from privileged system register accesses to generate an UNDEFINED exception"
