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LP-MSPM0G3507: Issues with MSPM0G3507: Fixed 2ns Offset in Dual ADC Synch Sampling @1MHz & Hanging in Infinite Loop at -O2

Part Number: LP-MSPM0G3507
Other Parts Discussed in Thread: MSPM0G3507

mspm0g3507 my problem.docxadc12_simultaneous_problem_file.zipHello TI Community Experts and Engineers,

 

I'm developing an application using the MSPM0G3507 MCU and encountered two distinct issues. I wonder if you could help me solve them:

 

Issue 1: Fixed Offset in Dual ADC Synchronous Sampling

 

Goal: Configure ADC0 and ADC1 for synchronous sampling at 1MHz sample rate.
Implementation:

 

  • Using a single trigger source (TIMA0) to initiate conversions on both ADCs.
  • Using separate DMA channels for each ADC to transfer results to two separate arrays (e.g., adc1_buffer[], adc2_buffer[]).
  • ADC configurations (clock source, resolution, sample-and-hold time, etc.) are identical. ADC clock source is ULPCLK(40MHz)

 

Problem:
After simultaneous conversion triggered at the same instant , comparing corresponding indexes in adc1_buffer[] and adc2_buffer[].
I observe a consistent fixed time offset between the sampled values at the same index position across the two arrays. Specifically, the value at index n in one array seems to correspond (in timing) to the value at index n+2 or n-2 in the other array, rather than index n to n. The estimated time difference is approximately 2 ns.

 

Could you help me figure out:
What are the potential causes of this fixed small offset? Could it be related to configuration (trigger synchronization granularity, DMA transfer initiation timing, memory access latency) or an inherent limitation within the chip's architecture?

Issue 2: Debugger Hangs in Infinite Loop at -O2 Optimization

 

Problem:
When compiling with optimization level -O0 (no optimization), the program runs correctly under the debugger (TI CCS / IAR).
When switching to optimization level -O2:

 

  • The program starts and runs under the debugger.
  • After running for some time (after Continue), when I attempt to pause it (Pause), the debugger fails to halt at the expected location.
  • The debugger shows the PC pointer stuck at address 0x00000414. Disassembly shows an instruction branching to itself (B 0x414), indicating the program has entered an unintended infinite loop.
  • The address 0x414 appears to be within a low memory region associated with the Reset_Handler flow, not within my main application loop.

 

Could you help me figure out:
Why would higher optimization cause the program to eventually become unresponsive and enter this loop? What are common root causes?
Could this expose undefined behavior (UB) in my code (e.g., uninitialized variables, memory corruption) that manifests differently with optimization?
Could it be related to interrupt handling, stack overflow, linker script configuration, or optimization of specific library functions?
What are effective strategies to debug such optimization-dependent hangs? (e.g., Map file analysis, specific compiler warnings?)

 

What I've Tried:

 

For Issue 1: Carefully verified ADC (trigger source, clock divider, sample timing) and DMA configurations (priority, trigger, source/destination, transfer mode) for both ADCs.

For Issue 2: Reviewed differences in generated code/output between -O0 and -O2 (disassembly, map file), but the exact root cause remains elusive. Enabled compiler warnings (-Wall).

 

Requesting Your Guidance:

 

For the dual ADC offset: What is the most likely cause of the 2ns discrepancy? How can I verify and resolve it?
For the -O2 hang: Could you suggest common troubleshooting steps or share relevant experiences?

 

Thank you very much for your time and assistance! I can provide specific configuration snippets (register settings, key functions) or project details if needed, while being mindful of security/IP.

 

Best regards,

  • You said:
    Could you help me figure out:
    What are the potential causes of this fixed small offset? Could it be related to configuration (trigger synchronization granularity, DMA transfer initiation timing, memory access latency) or an inherent limitation within the chip's architecture?

    0ns: ADC0 sampling, 1ns ADC1 sampling, 2ns ADC0 sampling, 3ns ADC1 sampling, here is the application, correct?

    How do you determine this small 2ns offset?

    From my point of view, there are small difference between two ADC's: ADC conversion error.

    With difference, you will get some ADC result error difference, these will cause result having some voltage level difference.

    You can try to calibrate the ADC error by input a DC signal.

    You said:
    Could you help me figure out:
    Why would higher optimization cause the program to eventually become unresponsive and enter this loop? What are common root causes?
    Could this expose undefined behavior (UB) in my code (e.g., uninitialized variables, memory corruption) that manifests differently with optimization?
    Could it be related to interrupt handling, stack overflow, linker script configuration, or optimization of specific library functions?
    What are effective strategies to debug such optimization-dependent hangs? (e.g., Map file analysis, specific compiler warnings?)

    Maybe some optimized code causing this.

    Never seen memory corruption from my side.

    If stack overflow influence some address variable, this will causing CPU enter hardfault.

    For interrupt, please try these two handler:

    void NMI_Handler(void)
    {
    __BKPT(0);
    }
    void HardFault_Handler(void)
    {
    __BKPT(0);
    }

    Maybe, M0 stuck in these two handlers, for NMI, you can read cause from this register: TRM: 1050h NMIIIDX NMI interrupt index in SYSCTL.

    Also, please add a __NOP(); at the first line of main while, to see whether fix the issue:

    while(1) {
    __asm("NOP");
    // Other app code here:
    app1();
    app2();
    }

    You said:
    For the -O2 hang: Could you suggest common troubleshooting steps or share relevant experiences?

    Check the address' function, read disassembly's accessing address(to confirm which peripherals)

    An old version 2*ADC 4MHz to get 8MHz sampling rate example for your reference:

    adc12_DualADC12to8MHz_DMA_LP_G3507_nortos_ticlang.zip

  • Thank you for your reply! However, there’s a slight clarification needed regarding the application scenario. Actually, I configured the two ADCs to sample simultaneously: for example, both ADC0 and ADC1 sample at 1ns, then both sample again at 2ns, and so on.

    The issue arises after the sampling results are stored in arrays: there’s a consistent offset, specifically that adc1_buffer[n] corresponds exactly to adc2_buffer[n+2]. This offset pattern also appears when I use the two ADCs to measure noise.

    I’m wondering what might be causing this fixed offset. Could you also advise on how to eliminate this offset? Looking forward to your insights. Thank you!

    0ns: ADC0 sampling, 1ns ADC1 sampling, 2ns ADC0 sampling, 3ns ADC1 sampling, here is the application, correct?

    感谢您的回复!不过关于应用场景,需要稍作澄清:我实际配置的是两个 ADC同时采样,例如 1ns 时 ADC0 和 ADC1 同时采样,2ns 时两者再次同时采样,以此类推。

    问题出在采样结果存入数组后:存在一个固定的偏移,具体表现为 adc1_buffer [n] 与 adc2_buffer [n+2] 完全对应。我用这两个 ADC 测量噪声时,也发现了同样的偏移规律。

    我想知道这种固定偏移可能是什么原因导致的,另外也想请教如何消除这个偏移?期待您的解答,谢谢!
  • 感谢您的回复,我发现当优化等级为2时加入__asm("NOP");可以正常调试,两个同步采样的波形无偏移,当不加入__asm("NOP");时程序无法进入while(1)内的判断语句,ADC会一直采样,不会停止。但当优化等级为0时,无论加不加__asm("NOP");波形都会有偏移

    Also, please add a __NOP(); at the first line of main while, to see whether fix the issue:
    此外,请在主 while 循环的第一行添加一个__NOP(); 以查看是否解决了问题:

    while(1) {
    __asm("NOP");
    // Other app code here:
    // 其他应用程序代码:

    app1();
    app2();
    }

    结合您提到的思路,我对目前的现象有了一些猜想,想和您确认一下:

    1. 优化等级为 2(-O2)时,编译器的深度优化可能导致了代码指令重排,使得 ADC 启动采样与 while (1) 内的判断逻辑出现了时序错位;而__asm("NOP")通过引入固定延迟,恰好抵消了这种错位,因此同步采样正常且程序能进入判断语句。反之,不加 NOP 时,时序错位导致判断逻辑失效,ADC 无法停止采样。
    2. 优化等级为 0(-O0)时,由于代码几乎不被优化,执行节奏松散且固定(比如指令按源码顺序执行的延迟、内存访问耗时等),使得两个 ADC 的实际采样时刻始终存在微小时差,且这种时差不受 NOP 的影响(可能因为 NOP 的延迟远小于无优化时的固有时序偏差),因此无论是否加 NOP,波形都会有偏移。

    不知道我的这些理解是否正确?想请您帮忙进一步验证或补充分析,非常感谢!
  • Now, it seems this is something related the software.

    1. You can use a 1:2 event channel, Event 12 Generic event channel 12 selected 1 : 2 (splitter)

    2. Use timer to trigger two ADC with channel 12.

    3. ADC connect ADC channel to CHANNEL A1_7 A0_7 (Same pin but connect to both ADC0 and ADC 1)

    You said
    I found that __asm ("NOP") is added when the optimization level is 2

    compiler issue (Known issue), can you send me your compiler version?

    Your understanding is correct, O2 will let the if after while disabled in assembly code.