请高手简单解释一下MSP430FR2311的时钟系统

han donglin

Prodigy 41 points

Other Parts Discussed in Thread: MSP430FR2311

刚入手MSP430FR2311，看过多次数据手册了，对它的时钟系统还没有理解透，如果我使用片内振荡器，如何让CPU 和AD工作在最快频率上？最好给个例程。谢了！（千万不要说再看看数据手册的话，如果能看明白，就不会在这问了）

8 年多前

0 Ling Zhu2 8 年多前

TI__Genius 17346 points

han donglin 说：

刚入手MSP430FR2311，看过多次数据手册了，对它的时钟系统还没有理解透，如果我使用片内振荡器，如何让CPU 和AD工作在最快频率上？最好给个例程。谢了！（千万不要说再看看数据手册的话，如果能看明白，就不会在这问了）

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//******************************************************************************
//  MSP430FR231x Demo - Configure MCLK for 16MHz operation, and REFO sourcing
//                                     FLLREF and ACLK. 
//
//  Description: Configure MCLK for 16MHz. FLL reference clock is REFO. At this 
//                    speed, the FRAM requires wait states. 
//                    ACLK = default REFO ~32768Hz, SMCLK = MCLK = 16MHz. 
//                    Toggle LED to indicate that the program is running.
//
//           MSP430FR2311
//         ---------------
//     /|\|               |
//      | |               |
//      --|RST            |
//        |          P1.2 |---> LED
//        |               |
//        |          P1.0 |---> SMCLK = 16MHz
//        |          P1.1 |---> ACLK  = 32768Hz
//
//
//   Darren Lu
//   Texas Instruments Inc.
//   July 2015
//   Built with IAR Embedded Workbench v6.30 & Code Composer Studio v6.1 
//******************************************************************************
#include <msp430.h>

int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;                          // Stop watchdog timer

    // Configure one FRAM waitstate as required by the device datasheet for MCLK
    // operation beyond 8MHz _before_ configuring the clock system.
    FRCTL0 = FRCTLPW | NWAITS_1;

    __bis_SR_register(SCG0);                           // disable FLL
    CSCTL3 |= SELREF__REFOCLK;                         // Set REFO as FLL reference source
    CSCTL0 = 0;                                        // clear DCO and MOD registers
    CSCTL1 &= ~(DCORSEL_7);                            // Clear DCO frequency select bits first
    CSCTL1 |= DCORSEL_5;                               // Set DCO = 16MHz
    CSCTL2 = FLLD_0 + 487;                             // DCOCLKDIV = 16MHz
    __delay_cycles(3);  
    __bic_SR_register(SCG0);                           // enable FLL
    while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1));         // FLL locked
    
    CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK;        // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
                                                       // default DCOCLKDIV as MCLK and SMCLK source

    P1DIR |= BIT0 | BIT1 | BIT2;                       // set ACLK SMCLK and LED pin as output
    P1SEL1 |= BIT0 | BIT1;                             // set ACLK and  SMCLK pin as second function

    PM5CTL0 &= ~LOCKLPM5;                              // Disable the GPIO power-on default high-impedance mode
                                                       // to activate previously configured port settings

    while(1)
    {
        P1OUT ^= BIT2;                                 // Toggle P1.2 using exclusive-OR
        __delay_cycles(8000000);                       // Delay for 8000000*(1/MCLK)=0.5s
    }
}