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MPS430F5529 mapping P4.1 P4.2 SPI模式应该怎么配置?

一直配置不成功

  • 使用2.7  ,   3.3  ,   3.4 的配置可以正常使用吗?

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    //******************************************************************************
    //   MSP430F552x Demo - USCI_A0, SPI 3-Wire Slave Data Echo
    //
    //   Description: SPI slave talks to SPI master using 3-wire mode. Data received
    //   from master is echoed back.  USCI RX ISR is used to handle communication,
    //   CPU normally in LPM4.  Prior to initial data exchange, master pulses
    //   slaves RST for complete reset.
    //   ACLK = ~32.768kHz, MCLK = SMCLK = DCO ~ 1048kHz
    //
    //   Use with SPI Master Incremented Data code example.  If the slave is in
    //   debug mode, the reset signal from the master will conflict with slave's
    //   JTAG; to work around, use IAR's "Release JTAG on Go" on slave device.  If
    //   breakpoints are set in slave RX ISR, master must stopped also to avoid
    //   overrunning slave RXBUF.
    //
    //                   MSP430F552x
    //                 -----------------
    //            /|\ |                 |
    //             |  |                 |
    //    Master---+->|RST              |
    //                |                 |
    //                |             P3.3|-> Data Out (UCA0SIMO)
    //                |                 |
    //                |             P3.4|<- Data In (UCA0SOMI)
    //                |                 |
    //                |             P2.7|-> Serial Clock Out (UCA0CLK)
    //
    //
    //   Bhargavi Nisarga
    //   Texas Instruments Inc.
    //   April 2009
    //   Built with CCSv4 and IAR Embedded Workbench Version: 4.21
    //******************************************************************************
    
    #include <msp430.h>
    
    int main(void)
    {
      WDTCTL = WDTPW+WDTHOLD;                   // Stop watchdog timer
    
      while(!(P2IN&0x80));                      // If clock sig from mstr stays low,
                                                // it is not yet in SPI mode
      P3SEL |= BIT3+BIT4;                       // P3.3,4 option select
      P2SEL |= BIT7;                            // P2.7 option select
      UCA0CTL1 |= UCSWRST;                      // **Put state machine in reset**
      UCA0CTL0 |= UCSYNC+UCCKPL+UCMSB;          // 3-pin, 8-bit SPI slave,
                                                // Clock polarity high, MSB
      UCA0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
      UCA0IE |= UCRXIE;                         // Enable USCI_A0 RX interrupt
    
      __bis_SR_register(LPM4_bits + GIE);       // Enter LPM4, enable interrupts
    }
    
    // Echo character
    #if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
    #pragma vector=USCI_A0_VECTOR
    __interrupt void USCI_A0_ISR(void)
    #elif defined(__GNUC__)
    void __attribute__ ((interrupt(USCI_A0_VECTOR))) USCI_A0_ISR (void)
    #else
    #error Compiler not supported!
    #endif
    {
      switch(__even_in_range(UCA0IV,4))
      {
        case 0:break;                             // Vector 0 - no interrupt
        case 2:                                   // Vector 2 - RXIFG
          while (!(UCA0IFG&UCTXIFG));             // USCI_A0 TX buffer ready?
          UCA0TXBUF = UCA0RXBUF;
          break;
        case 4:break;                             // Vector 4 - TXIFG
        default: break;
      }
    }