在用MSP420F5529LP产生SPWM时周期性出现错误波形,具体波形及代码如下图所示,
#include <msp430.h>
unsigned char nCount=0;
unsigned int Sintable[] =
{25,50,75,100,125,150,175,200,225,
250,275,299,324,349,373,397,422,446,470,
494,518,541,565,588,612,635,658,681,703,
726,748,770,792,814,835,857,878,899,920,
940,960,980,1000,1019,1039,1058,1076,1095,1113,
1131,1149,1166,1183,1200,1216,1232,1248,1264,1279,
1294,1309,1323,1337,1350,1364,1377,1389,1402,1414,
1425,1436,1447,1458,1468,1478,1487,1496,1505,1513,
1521,1529,1536,1543,1549,1555,1561,1566,1571,1576,
1580,1584,1587,1590,1592,1595,1596,1598,1599,1599,
1600,1599,1599,1598,1596,1595,1592,1590,1587,1584,
1580,1576,1571,1566,1561,1555,1549,1543,1536,1529,
1521,1513,1505,1496,1487,1478,1468,1458,1447,1436,
1425,1414,1402,1389,1377,1364,1350,1337,1323,1309,
1294,1279,1264,1248,1232,1216,1200,1183,1166,1149,
1131,1113,1095,1076,1058,1039,1019,1000,980,960,
940,920,899,878,857,835,814,792,770,748,
726,703,681,658,635,612,588,565,541,518,
494,470,446,422,397,373,349,324,299,275,
250,225,200,175,150,125,100,75,50,25};
void Init_CLK(void)
{
P1DIR |= BIT0;
P1SEL |= BIT0; //可以看ACLK的频率
P2DIR |= BIT2;
P2SEL |= BIT2; //SMCLK
P7DIR |= BIT7;
P7SEL |= BIT7; //MCLK
P5SEL |= BIT2+BIT3;
UCSCTL6 &= ~XT2OFF; //打开XT2
/*********************寄存器配置部分******************************/
__bis_SR_register(SCG0);
UCSCTL0 = DCO0+DCO1+DCO2+DCO3+DCO4;
UCSCTL1 = DCORSEL_4; //DCO频率范围在28.2MHZ以下
UCSCTL2 = FLLD_4 + 1; //D=16,N=1
UCSCTL3 = SELREF_5 + FLLREFDIV_3; //n=8,FLLREFCLK时钟源为XT2CLK;DCOCLK=D*(N+1)*(FLLREFCLK/n);DCOCLKDIV=(N+1)*(FLLREFCLK/n);
UCSCTL4 = SELA_4 + SELS_3 +SELM_3; //ACLK的时钟源为DCOCLKDIV,MCLK\SMCLK的时钟源为DCOCLK
UCSCTL5 = DIVA_5; //ACLK由DCOCLKDIV的32分频得到,SMCLK由DCOCLK的2分频得到
//最终MCLK:16MHZ,SMCLK:8MHZ,ACLK:32KHZ
__bic_SR_register(SCG0); //Enable the FLL control loop
/**********************************************************************/
__delay_cycles(8192);
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); //Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; //Clear fault flags
}while (SFRIFG1&OFIFG);
}
void Timer_A0_Init(void)
{
P1DIR |= BIT2;
P1SEL |= BIT2;
TA0CCR0 = (1600 - 1);
TA0CCTL0 = CCIE;
TA0CCR1 = Sintable[0];
TA0CCTL1 = OUTMOD_7;
TA0CTL = TASSEL_2 + MC_1 + TACLR;
}
void main()
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
Init_CLK();
Timer_A0_Init();
_EINT();
while(1);
}
//#pragma vector=TIMER1_A0_VECTOR
//__interrupt void TIMER1_A0_ISR(void)
#pragma vector=TIMER0_A0_VECTOR
__interrupt void TIMER0_A0_ISR(void)
{
nCount++;
if(nCount >= 200)
nCount = 0;
TA0CCR1 = Sintable[nCount];
}