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MSP430F6736 SD24增益设置问题

user402656248
Prodigy 30 points
Other Parts Discussed in Thread: MSP430F6736

求助：MSP430F6736使用SD24进行ADC采集，发现增益设置为SD24GAIN_64或者SD24GAIN_128时，读取到的转换结果都为0，但设置SD24GAIN_32或者SD24GAIN_8就是对的。代码设置如下：

SD24BCTL0 = SD24SSEL_0|SD24REFS; // Select MCLK as SD24_B clock source|Selectinternal REF
SD24BCTL1_H = SD24DMA_0;
SD24BINCTL0 |= SD24INTDLY_1|SD24GAIN_128; //
SD24BOSR0=800; //
SD24BCCTL0 |= SD24SCS0 + SD24SNGL + SD24ALGN;

请各位大侠帮忙看看是哪里错了，谢谢。

  • 0
    TI__Guru**** 252096 points

    请您参考一下数据手册内的说明，目前您的设计是否符合要求：

    Table 5-39. SD24_B, Power Supply and Operating Conditions

    (1) The full-scale range (FSR) is defined by VFS+ = +VREF/GAIN and VFS– = –VREF/GAIN: FSR = VFS+ – VFS– = 2 × VREF/GAIN. If VREF is
    sourced externally, the analog input range should not exceed 80% of VFS+ or VFS–, that is, VID = 0.8 VFS– to 0.8 VFS+. If VREF is sourced
    internally, the given VID ranges apply. MIN values are calculated based on a VREF of 1.125 V. TYP values are calculated based on a
    VREF of 1.16 V.