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CS_setDCOFreq(CS_DCORSEL_1,CS_DCOFSEL_3); //High range and 8MHz CS_initClockSignal(CS_MCLK,CS_DCOCLK_SELECT,CS_CLOCK_DIVIDER_1); CS_initClockSignal(CS_SMCLK,CS_DCOCLK_SELECT,CS_CLOCK_DIVIDER_1); // Configure wait states to be able to use 8 MHz MCLK FRCTL0 = (FRCTLPW | NWAITS_0); __delay_cycles(16000); __disable_interrupt(); // to eliminate echo of int8_ts ((void (*)())0x1000)(); // jump to Z-area of BSL
#include <msp430.h>
#include <stdbool.h>
#include <stdint.h>
/**
* main.c
*/
int main(void)
{
WDTCTL = WDTPW | WDTHOLD; // stop watchdog timer
// GPIO initialization specific to HW
P1DIR = (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7);
P1OUT = 0x00;
P1SEL0 = (BIT2 | BIT3);
P2DIR = (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT6 | BIT7);
// enable pullup on P2
P2OUT = BIT5;
P2REN = BIT5;
PM5CTL0 &= ~LOCKLPM5;
// FIRST START UP AT 16MHZ
// Configure one FRAM waitstate as required by the device datasheet for MCLK
// operation beyond 8MHz _before_ configuring the clock system.
FRCTL0 = FRCTLPW | NWAITS_1;
// Clock System Setup
CSCTL0_H = CSKEY_H; // Unlock CS registers
CSCTL1 = DCOFSEL_0; // Set DCO to 1MHz
// Set SMCLK = MCLK = DCO, ACLK = VLOCLK
CSCTL2 = SELA__VLOCLK | SELS__DCOCLK | SELM__DCOCLK;
// Per Device Errata set divider to 4 before changing frequency to
// prevent out of spec operation from overshoot transient
CSCTL3 = DIVA__4 | DIVS__4 | DIVM__4; // Set all corresponding clk sources to divide by 4 for errata
CSCTL1 = DCOFSEL_4 | DCORSEL; // Set DCO to 16MHz
// Delay by ~10us to let DCO settle. 60 cycles = 20 cycles buffer + (10us / (1/4MHz))
__delay_cycles(60);
CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1; // Set all dividers to 1 for 16MHz operation
CSCTL0_H = 0; // Lock CS registers // Lock CS registers
// THEN DROP DOWN TO 8MHZ BEFORE INVOKING BSL
__delay_cycles(16000000);
CSCTL0_H = CSKEY_H; // Unlock CS registers
CSCTL1 = DCOFSEL_0; // Set DCO to 1MHz
// Per Device Errata set divider to 4 before changing frequency to
// prevent out of spec operation from overshoot transient
CSCTL3 = DIVA__4 | DIVS__4 | DIVM__4; // Set all corresponding clk sources to divide by 4 for errata
CSCTL1 = DCOFSEL_3 | DCORSEL; // Set DCO to 8MHz
// Delay by ~10us to let DCO settle. 60 cycles = 20 cycles buffer + (10us / (1/4MHz))
__delay_cycles(60);
CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1; // Set all dividers to 1 for 16MHz operation
CSCTL0_H = 0; // Lock CS registers // Lock CS registers
// Configure zero FRAM waitstate as required by the device datasheet for MCLK
FRCTL0 = FRCTLPW | NWAITS_0;
while(1)
{
// Toggle LED1 to signal application is running
P1OUT ^= BIT0;
// If switch is pressed, enter BSL mode
if((P2IN & BIT5) != BIT5)
{
// Set LED2 to signal entry into BSL
P1OUT |= BIT1;
((void (*)())0x1000) ();
}
_delay_cycles(1000000);
}
}
