MSP430FR5043: BSL频率问题

您好，因为工程师这边没办法重现该问题，您能否尝试将代码大小降至绝对最小值，然后看下问题是否仍然存在？以下为工程师的项目，您可以参考下：

#include <msp430.h> 
#include <stdbool.h>
#include <stdint.h>



/**
 * main.c
 */
int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;	// stop watchdog timer
	
	// GPIO initialization specific to HW
    P1DIR = (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7);
    P1OUT = 0x00;
    P1SEL0 = (BIT2 | BIT3);

    P2DIR  = (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT6 | BIT7);
    // enable pullup on P2
    P2OUT  = BIT5;
    P2REN  = BIT5;

    PM5CTL0 &= ~LOCKLPM5;

    // FIRST START UP AT 16MHZ
    // Configure one FRAM waitstate as required by the device datasheet for MCLK
    // operation beyond 8MHz _before_ configuring the clock system.
    FRCTL0 = FRCTLPW | NWAITS_1;

    // Clock System Setup
    CSCTL0_H = CSKEY_H;                     // Unlock CS registers
    CSCTL1 = DCOFSEL_0;                     // Set DCO to 1MHz
    // Set SMCLK = MCLK = DCO, ACLK = VLOCLK
    CSCTL2 = SELA__VLOCLK | SELS__DCOCLK | SELM__DCOCLK;
    // Per Device Errata set divider to 4 before changing frequency to
    // prevent out of spec operation from overshoot transient
    CSCTL3 = DIVA__4 | DIVS__4 | DIVM__4;   // Set all corresponding clk sources to divide by 4 for errata
    CSCTL1 = DCOFSEL_4 | DCORSEL;           // Set DCO to 16MHz
    // Delay by ~10us to let DCO settle. 60 cycles = 20 cycles buffer + (10us / (1/4MHz))
    __delay_cycles(60);
    CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;   // Set all dividers to 1 for 16MHz operation
    CSCTL0_H = 0;                           // Lock CS registers                      // Lock CS registers

    // THEN DROP DOWN TO 8MHZ BEFORE INVOKING BSL
    __delay_cycles(16000000);

    CSCTL0_H = CSKEY_H;                     // Unlock CS registers
    CSCTL1 = DCOFSEL_0;                     // Set DCO to 1MHz
    // Per Device Errata set divider to 4 before changing frequency to
    // prevent out of spec operation from overshoot transient
    CSCTL3 = DIVA__4 | DIVS__4 | DIVM__4;   // Set all corresponding clk sources to divide by 4 for errata
    CSCTL1 = DCOFSEL_3 | DCORSEL;           // Set DCO to 8MHz
    // Delay by ~10us to let DCO settle. 60 cycles = 20 cycles buffer + (10us / (1/4MHz))
    __delay_cycles(60);
    CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;   // Set all dividers to 1 for 16MHz operation
    CSCTL0_H = 0;                           // Lock CS registers                      // Lock CS registers

    // Configure zero FRAM waitstate as required by the device datasheet for MCLK

      FRCTL0 = FRCTLPW | NWAITS_0;


      while(1)
      {
          // Toggle LED1 to signal application is running
          P1OUT ^= BIT0;

          // If switch is pressed, enter BSL mode
          if((P2IN & BIT5) != BIT5)
          {
              // Set LED2 to signal entry into BSL
              P1OUT |= BIT1;
             ((void (*)())0x1000) ();
          }

          _delay_cycles(1000000);
      }

}

非常感谢！我试着加上了改变频率之前的降低到1MHz并且把分频设置为4，现在可以完美运行在16MHz下并且用8MHz进行BSL了。

再麻烦问下，这个errata在哪里可以找到呢，应该是我没有留意这个errata所以一直没有解决这个问题