msp430uart串口与电脑通信,430串口时钟选为32.768KHz,波特率为19200,以下寄存器中的值该如何设置?
UCA3CTL1 |= UCSSEL_1; // CLK = ACLK
UCA3BR0 = 0x01; // 32kHz/19200= 1.7
UCA3BR1 = ? //
UCA3MCTL = ?
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msp430uart串口与电脑通信,430串口时钟选为32.768KHz,波特率为19200,以下寄存器中的值该如何设置?
UCA3CTL1 |= UCSSEL_1; // CLK = ACLK
UCA3BR0 = 0x01; // 32kHz/19200= 1.7
UCA3BR1 = ? //
UCA3MCTL = ?
以下是摘自e2e论坛的回答
However, 32768/19200 is1.7, so the first bit would be 1/32768s, the next one 2/32768s, then again 1/32768s etc. The resulting bitlenght-error will be far, far beyond any acceptable limit.
With higher frequencies, the divider gets larger, and the difference between UCBR and UCBR+1 gets smaller, so the maximum bitrate error gets smaller. Or the baudrate can be higher. The maximum baudrate for the USCI is IMHO 1MBd. A faster clock source will not allow higher baudrates, only a higher divider and therefore a smaller error (if it isn't an exact multiple anyway). or allow the 16x overclocking