MSP430F5529 ADC12 编译不过！求解释！！！

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Other Parts Discussed in Thread: MSP430F5529

/*
* AD_main.c
*
* Created on: 2013-8-4
* Author: Administrator
*/

#include<msp430f5529.h>
#include"HAL_Board.h"

#define num_results 512
int results[num_results] = {0};
void ADC_Init(void);

void main(void)
{
WDTCTL=WDTPW+WDTHOLD;//关闭看门狗
Board_init(); //初始化GPIO
ADC_Init();//ADC初始化
ADC12CTL0 |=ADC12ENC;//AD转换允许
LPM0;//进入低功耗模式0
}

void ADC_Init(void)
{
P8DIR |=BIT1;//P8.1为输出，即led2
P8OUT &=~BIT1;//led2灭
    P6SEL |=BIT0;//打开AD模拟端口A0
//配置ADC12
    ADC12CTL0 = ADC12ON+ADC12SHT02+ADC12REF2_5V+ADC12REFON ;
    //打开ADC12内核，采样保持时间系数2，选择内部参考电压2.5v，打开内部参考电压发生器
    ADC12CTL1 = ADC12SHP+ADC12CONSEQ_2+ADC12SHS_1;
    //采样定时器作为采样触发信号源SAMPCON，由采样输入信号ADC12CLK的上升沿触发采样定时器
    //单通道多次采样，采样触发源为TIMERA的输出单元out1输出的信号（由CCR1定时产生）
    ADC12MCTL0 =ADC12INCH_0+ADC12SREF_1;
    //选择0通道，参考电压源为：v+=Vref+,v-=Avss
    ADC12IE |=BIT0;//开中断允许ADC12IFG.0

//配置定时器
    TA0CCR0 =1500;//延时
    TA0CCTL0 |=CCIE;//开定时器中断允许，定时器为比较模式
    TA0CTL = TASSEL_1 | MC_1;//TACLK=ACLK,增计数模式
    LPM3;
    TA0CCTL0 &=~CCIE;//关闭定时器捕获比较中断

P1SEL |=BIT2;//开TA0.1作为TIMERA_out1的输出功能
P1DIR |=BIT2;//输出

TA0CCR0 = 7;//初始化TA0CCL0,采样时钟周期=CCR0+1

TA0CCR1 = 4;
//初始化TA0CCL1,用于产生一个TIMERA_out1信号给ADC12做采样触发信号源

TA0CCTL1 =OUTMOD_3;
//CCR1捕获比较寄存器的out1输出单元为置位/复位模式

TA0CTL =TACLR | MC_1 |TASSEL_1;
//清除TA，增计数模式，定时器时钟为ACLK
}

#pragma vector=ADC12_VECTOR
__interrupt void ADC12ISR(void)
{
static unsigned int index =0; //静态变量

    switch(__even_in_range(ADC12IV,34))
    {
    case 0: break;                           // Vector 0: No interrupt
    case 2: break;                           // Vector 2: ADC overflow
    case 4: break;                           // Vector 4: ADC timing overflow
    case 6:                           // Vector 6: ADC12IFG0
    results[index++]=ADC12MEM0;//移动ADC结果到数组，此时ADC12IFG.0自动复位

         if(index==512)
           {
         ADC12CTL0 &=~ADC12ENC;// 停止转换
         index=0;
         P8OUT |=BIT1;
         LPM3;
           }
    case 8: break;                           // Vector 8: ADC12IFG1
    case 10: break;                           // Vector 10: ADC12IFG2
    case 12: break;                           // Vector 12: ADC12IFG3
    case 14: break;                           // Vector 14: ADC12IFG4
    case 16: break;                           // Vector 16: ADC12IFG5
    case 18: break;                           // Vector 18: ADC12IFG6
    case 20: break;                           // Vector 20: ADC12IFG7
    case 22: break;                           // Vector 22: ADC12IFG8
    case 24: break;                           // Vector 24: ADC12IFG9
    case 26: break;                           // Vector 26: ADC12IFG10
    case 28: break;                           // Vector 28: ADC12IFG11
    case 30: break;                           // Vector 30: ADC12IFG12
    case 32: break;                           // Vector 32: ADC12IFG13
    case 34: break;                           // Vector 34: ADC12IFG14
    default: break;
    }
}