MSP430F5529 ADC12代码疑问

#include <msp430.h> 
#include "./Include/HAL_Dogs102x6.h"
#include "./Include/HAL_Board.h"

#define Num_Results 8

int ADC_Results[Num_Results];
/*
 * main.c
 */
int main(void) {
	volatile unsigned int  i;


	WDTCTL = WDTPW + WDTHOLD;
	P1DIR |= BIT0;
	P1SEL |= BIT0;                            // Timer_A
	P2SEL |= BIT2;
	P2DIR |= BIT2;                            // Test SMCLK
	P6SEL |= BIT6;
	P6DIR &= ~BIT6;

	P5SEL |= BIT4 + BIT5; 					  // Port select XT1
	REFCTL0 &= ~REFMSTR;

	UCSCTL6 &= ~(XT1OFF);                     // XT1 On
	UCSCTL6 |= XCAP_3;                        // Internal load cap

	// Loop until XT1 fault flag is cleared
	do
	{
	  UCSCTL7 &= ~XT1LFOFFG;                  // Clear XT1 fault flags
	}while (UCSCTL7&XT1LFOFFG);               // Test XT1 fault flag

	// Initialize DCO to 0.7MHz
	__bis_SR_register(SCG0);                  // Disable the FLL control loop
	UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx
	UCSCTL1 = DCORSEL_1;
	UCSCTL2 = FLLD_1 + 21;                    // Set DCO Multiplier for 0.7MHz
	                                          // (N + 1) * FLLRef = Fdco
	                                          // (21 + 1) * 32768 = 0.7MHz
	                                          // Set FLL Div = fDCOCLK/2
	UCSCTL3 = SELREF_2 + FLLREFDIV_0;
	UCSCTL4 = SELA_0 + SELS_3 + SELM_3;
	UCSCTL5 = DIVPA_0 + DIVA_0 + DIVS_0 + DIVM_0;

	__bic_SR_register(SCG0);                  // Enable the FLL control loop

	// 32 x 32 x 0.7 MHz / 32,768 Hz = 21875 = MCLK cycles for DCO to settle
	__delay_cycles(21875);

	do
	{
	   UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags
	   SFRIFG1 &= ~OFIFG;                      	// Clear fault flags
	}while (SFRIFG1&OFIFG);                   	// Test oscillator fault flag


	ADC12CTL0 = ADC12ON + ADC12SHT0_15 + ADC12REFON + ADC12REF2_5V;	// ADC On, 1024 ADC12CLK Cycles, ADC Voltage Reference On, Voltage Reference 2.5V
    ADC12CTL1 = ADC12CONSEQ_2 + ADC12CSTARTADD_0 + ADC12SHS_1;    	// Repeat Single-Channel Conversion, Conversion memory start address
	ADC12CTL2 = ADC12RES_2;											// ADC12 resolution 12 bits
	ADC12MCTL0 |= ADC12INCH_6 + ADC12SREF_1;						// ADC Input select, V(R+) = VREF+ and V(R-) = AVSS
    while (REFCTL0 & REFGENBUSY)									// If Ref generator busy, wait
    	REFCTL0 |= REFVSEL_2 + REFON;								// Select internal Ref = 2.5V, Internal Reference On

    TA0CTL = TASSEL_2 + MC_1 + TACLR;			// Choose SMCLK, Up-Mode, Clear TAR
	TA0CCR0 = 6;								// 0.7MHz/100KHz - 1 = 6
	TA0CCTL0 = CAP + CCIE + CCIFG;

	for(i = 0; i < 0x30; i++)
	
	ADC12CTL0 |= ADC12ENC;
	while (1){
		ADC12CTL0 |= ADC12SC;
		while(!(ADC12IFG & BIT0));
		__no_operation();
    }

	__bis_SR_register(LPM3_bits + GIE);
}

#pragma vector=ADC12_VECTOR
__interrupt void ADC12ISR (void)
{
  static unsigned int index = 0;

  switch(__even_in_range(ADC12IV,34))
  {
  	  case  0: break;                           // Vector  0:  No interrupt
  	  case  2: break;                           // Vector  2:  ADC overflow
  	  case  4: break;                           // Vector  4:  ADC timing overflow
  	  case  6: break;                           // Vector  6:  ADC12IFG0
  	  case  8: break;                           // Vector  8:  ADC12IFG1
  	  case 10: break;                           // Vector 10:  ADC12IFG2
  	  case 12:                                  // Vector 12:  ADC12IFG3
  	  {
  		  ADC_Results[index] = ADC12MEM0;
  		  Board_ledOn(LED1);					// Test by LED1
  		  index ++;
  		  if (index == 8)
  		  {
			index = 0;
  		  }
  	  }
  	  case 14: break;                           // Vector 14:  ADC12IFG4
  	  case 16: break;                           // Vector 16:  ADC12IFG5
  	  case 18: break;                           // Vector 18:  ADC12IFG6
  	  case 20: break;                           // Vector 20:  ADC12IFG7
  	  case 22: break;                           // Vector 22:  ADC12IFG8
  	  case 24: break;                           // Vector 24:  ADC12IFG9
  	  case 26: break;                           // Vector 26:  ADC12IFG10
  	  case 28: break;                           // Vector 28:  ADC12IFG11
  	  case 30: break;                           // Vector 30:  ADC12IFG12
  	  case 32: break;                           // Vector 32:  ADC12IFG13
  	  case 34: break;                           // Vector 34:  ADC12IFG14
  	  default: break;
  }
}