1、测量Vcore电压为1.9V,没有升压成功;
2、SMCLK晶振一直显示12M频率,而且无法通过配置改变。
int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
SetVcoreUp(PMMCOREV_1);
SetVcoreUp(PMMCOREV_2); // Set VCore to 24MHz for 32MHz
SetVcoreUp(PMMCOREV_3);
P11DIR = BIT1+BIT2+BIT0; // P11.1-2 to output direction
P11SEL |= BIT0+BIT1+BIT2; // P11.1-2 to output SMCLK,MCLK
P5SEL |= 0x0C; // Port select XT2
UCSCTL6 &= ~XT2OFF; // Enable XT1,XT2
UCSCTL3 |= SELREF_2;
// Since LFXT1 is not used,
// sourcing FLL with LFXT1 can cause
// XT1OFFG flag to set
UCSCTL4 |= SELA_2; // ACLK=REFO,32.768khz
__bis_SR_register(SCG0); // 关闭 FLL
UCSCTL0 = 31; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_7; // Select DCO range 25MHz operation
UCSCTL6 |= XT2DRIVE_3;
UCSCTL3 |= (FLLREFDIV_4+SELREF_5); //分频至1MHZ,使用XT2
UCSCTL2 = FLLD_2 + 24; //Fdco=(N + 1) * FLLrefdiv Set FLL Div = fDCOCLK/4
__bic_SR_register(SCG0); // 打开 FLL
__delay_cycles(782000);
UCSCTL4 |= SELS_2 + SELM_3;
// Loop until XT1,XT2 & DCO stabilizes
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
// expected frequency
while(1); // Loop in place
}