MSP430FR2433: reset 复位的总时间是多少？

weifeng he

Prodigy 10 points

Part Number: MSP430FR2433

我目前看波形发现芯片掉电到1.4V后，重现上电到跑进程序需要20ms左右的时间，有没有办法可以缩短上电进入程序的时间

int main(void)
{

Init_MCU();
Init_CLOCKS();

// SFRRPCR=0x000c;

P1SEL0 |= BIT2 | BIT3;
CE_7100_SET_OUT;
CE_7100_OUT_0;
CE_7100_OUT_1;CE_7100_OUT_0;
SYSCFG0 = FRWPPW | DFWP;

if(Write_flag.mode == cmd03nack)
Write_flag.count.CMD03 ++;
if(Write_flag.count.CMD03 == 2)
Write_flag.mode = normal;
if(Write_flag.mode != cmd03nack)
Init_IIC(Box_ID);

//Tim初始化
g_sn_change.tim_count=0; //clear
g_sn_change.Check_ID0105_flag=0;
g_sn_change.VDD_START_FLAG=0;
if(attest_flag==5)
{
Init_TIM(); //关闭TIM
TA0CTL |= TASSEL_2+MC_1+ID_2; //设置定时器计数模式开启
TA0CCTL0 = CCIE;
g_sn_change.tim_count=0;
g_sn_change.Check_ID0105_flag==1;
}
else if(attest_flag!=6)
{
Init_TIM(); //关闭TIM
attest_flag=0;
}
Change_ID=ID_BUF[ID_NUM]; //每次上电，确认当前码表的ID
DATA_7100_SET_OUT;
DATA_7100_OUT_0;

// CE_7100_SET_OUT;
CLK_7100_SET_OUT;
CLK_7100_OUT_0;
CE_7100_OUT_0;
// delay_us(100);
CE_7100_OUT_1;CE_7100_OUT_0;

// if(CJ7100_start_flag==1)
// {
// VDD_7100_SET_OUT;
// memset(Check_cj7100sn, 0, sizeof(Check_cj7100sn));
// while(CJ7100_start_flag==1) //7100数据异常，重新debug写码
// {
// VDD_7100_OUT_0;delay_ms(20); CJ7100_DEBUG_RST();
//
// f_7100_SN();
// if(strncmp(FRAM_write+0x440,Check_cj7100sn,12)==0)
// {
// CJ7100_start_flag=0;
// }
// else {
// CJ7100_start_flag=1;
// }
// }
// }

SYSCFG0 = FRWPPW | PFWP | DFWP;

while (1)

{

}

2 年多前

0 weifeng he 2 年多前

Prodigy 10 points

void Init_CLOCKS(void)
{
// Configure one FRAM waitstate as required by the device datasheet for MCLK
// operation beyond 8MHz before configuring the clock system.
FRCTL0 = FRCTLPW | NWAITS_1; //Change the NWAITS_1 value to add the right amount of waitstates
__bis_SR_register(SCG0); // disable FLL
CSCTL3 |= SELREF__REFOCLK; // Set REFO as FLL reference source，P116
CSCTL0 = 0; // clear DCO and MOD registers
CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first
CSCTL1 |= DCORSEL_5; // Set DCO = 16MHz
CSCTL2 = FLLD_0 + 487; // DCOCLKDIV = 16MHz ，000b = fDCOCLK ÷ 1，487=0X01E7=0000 0001 1110 0111
__delay_cycles(3);
__bic_SR_register(SCG0); // enable FLL
// Disable waiting FLL lock, as it takes about 300ms in active mode.
// Just go to sleep and work with unlocked clock during first operations.
// while(CSCTL7 & (FL LUNLOCK0 | FLLUNLOCK1)); // FLL locked
CSCTL4 = SELMS__DCOCLKDIV; // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
// default DCOCLKDIV as MCLK and SMCLK source
}

void Init_MCU(void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop WDT
// Disable the GPIO power-on default high-impedance mode
// to activate previously configured port settings
PM5CTL0 &= ~LOCKLPM5;
}