在软件触发DMA1转移数据时会干扰DMA0转移数据，导致DMA0无法转移ADC新转换的第一个新数据，产生ADC12OVIE中断，将这个软件触发取消之后一切正常，没有ADC中断产生，请问当一个DMA通道连续重复转移一个数据点，另一个通道转移256点的数据块时，会有干扰吗？这种情况是正常的吗？
#include <msp430.h>
#include <stdio.h>
#include <stdint.h>
volatile int buf[512];
/*volatile int buf2[256];*/
volatile int result[256];
unsigned char bufflag=1;
unsigned char DMA0flag=1;
unsigned char DMA2flag=1;
void GPIO_INIT(){
/*Configure GPIOs to it's lowest power state*/
P1OUT = 0;
P1DIR = 0xFF;
P2OUT = 0;
P2DIR = 0xFF;
P3OUT = 0;
P3DIR = 0xFF;
P4OUT = 0;
P4DIR = 0xFF;
P5OUT = 0;
P5DIR = 0xFF;
P6OUT = 0;
P6DIR = 0xFF;
P7OUT = 0;
P7DIR = 0xFF;
P8OUT = 0;
P8DIR = 0xFF;
PJOUT = 0;
PJDIR = 0xFFFF;
P1SEL0 |= BIT3; // 配置1.3引脚为AD输入通道
P1SEL1 |= BIT3;
/* Output SMCLK,观察时钟源变化*/
P3DIR |= BIT4;
P3SEL1 |= BIT4;
P3SEL0 |= BIT4;
/* Disable the GPIO power-on default high-impedance mode to activate previously configured port settings*/
PM5CTL0 &= ~LOCKLPM5;
}
void CLOCK_init(){
/*Clock System Setup*/
CSCTL0_H = CSKEY_H; // Unlock CS registers
CSCTL1 = DCOFSEL_0; // Set DCO to 1MHz
CSCTL2 = SELA__VLOCLK | SELS__DCOCLK | SELM__DCOCLK;
// Per Device Errata set divider to 4 before changing frequency to
// prevent out of spec operation from overshoot transient
CSCTL3 = DIVA__4 | DIVS__4 | DIVM__4; // Set all corresponding clk sources to divide by 4 for errata
CSCTL1 = DCOFSEL_6; // Set DCO to 8MHz
// Delay by ~10us to let DCO settle. 60 cycles = 20 cycles buffer + (10us / (1/4MHz))
__delay_cycles(60);
CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1; // Set all dividers
CSCTL0_H = 0; // Lock CS Registers
}
void TIMER_init(){
TB0CCR0 = 250; /* PWM 周期*/
TB0CCTL1 = OUTMOD_7; /* 定时器A的输出工作模式*/
TB0CCR1 = 10; /* PWM高电平占空比*/
TB0CTL = TASSEL__SMCLK | MC__UP | TACLR; /*定时器时钟源SMCLK，开启定时器*/
}
void ADC12_init(){
ADC12CTL0 = ADC12SHT0_2 | ADC12ON; // Sampling time, S&H=16(4个采样保持AD时钟周期), ADC12 on开启AD
ADC12CTL1 = ADC12SHP | ADC12SHS_3 | ADC12CONSEQ_2 | ADC12SSEL_3;
// A1 ADC input select; Vref+ = AVCC 中断源选择，选择A3通道，序列未结束，参考电压默认没有设置
ADC12MCTL0 = ADC12INCH_3 | ADC12EOS;
ADC12CTL2 |= ADC12RES_2; //转换的位数12
// ADC12IER0 |= ADC12IE0; // Enable ADC interrupt 使能ADC12IFGO中断
ADC12IER2 |= ADC12TOVIE; //使能ADC转换时间溢出中断
ADC12IER2 |= ADC12OVIE; //使能MEM缓存存储器溢出中断位
ADC12CTL0 |= ADC12ENC ; // Start sampling/conversion 开启AD转换
}
int main(void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop WDT
GPIO_INIT();
CLOCK_init();
TIMER_init();
ADC12_init();
// Configure DMA channel 0
__data20_write_long((uintptr_t) &DMA0SA,(uintptr_t) &ADC12MEM0);
// Source block address
__data20_write_long((uintptr_t) &DMA0DA,(uintptr_t) &buf[0]);
// Destination single address
DMA0SZ = 256; // Block size
DMACTL0 |= DMA0TSEL_26;
DMA0CTL = DMADT_4 | DMASRCINCR_0 | DMADSTINCR_3; // Rpt, inc
DMA0CTL |= DMAEN | DMAIE; // Enable DMA0
__data20_write_long((uintptr_t) &DMA1SA,(uintptr_t) &buf[0]);
__data20_write_long((uintptr_t) &DMA1DA,(uintptr_t) &result);
DMA1SZ = 256; // Block size
DMA1CTL = DMADT_1 | DMASRCINCR_3 | DMADSTINCR_3; // Rpt, inc
DMA1CTL |= DMAEN ;
__bis_SR_register(GIE); // LPM0, ADC12_ISR will force exit
while(1)
{
if(DMA0flag==2){
switch(bufflag){
case 1:
// DMA1CTL |= DMAREQ;
DMA0flag=1;
DMA1CTL &= ~DMAEN;
__data20_write_long((uintptr_t) &DMA1SA,(uintptr_t) &buf[0]);
DMA1CTL |= DMAEN ;
break;
case 2:
// DMA1CTL |= DMAREQ;
DMA0flag=1;
DMA1CTL &= ~DMAEN;
__data20_write_long((uintptr_t) &DMA1SA,(uintptr_t) &buf[256]);
DMA1CTL |= DMAEN ;
break;
}
__no_operation();
}
}
}
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=DMA_VECTOR
__interrupt void DMA_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(DMA_VECTOR))) DMA_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(DMAIV,16))
{
case 0: break;
case 2: // DMA0IFG = DMA Channel 0
DMA0CTL &= ~DMAEN;
if(bufflag==1){
__data20_write_long((uintptr_t) &DMA0DA,(uintptr_t) &buf[256]);
DMA0CTL |= DMAEN | DMAIE;
bufflag=2;
}
else if(bufflag==2){
__data20_write_long((uintptr_t) &DMA0DA,(uintptr_t) &buf[0]);
DMA0CTL |= DMAEN | DMAIE;
bufflag=1;
}
DMA0flag=2;
// __bic_SR_register_on_exit(LPM0_bits); // Exit active CPU
break;
case 4: // DMA1IFG = DMA Channel 1
P1OUT ^= BIT0;
break;
case 6: break; // DMA2IFG = DMA Channel 2
case 8: break; // DMA3IFG = DMA Channel 3
case 10: break; // DMA4IFG = DMA Channel 4
case 12: break; // DMA5IFG = DMA Channel 5
case 14: break; // DMA6IFG = DMA Channel 6
case 16: break; // DMA7IFG = DMA Channel 7
default: break;
}
}
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=ADC12_B_VECTOR
__interrupt void ADC12ISR (void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC12_B_VECTOR))) ADC12ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(ADC12IV, ADC12IV__ADC12RDYIFG))
{
case ADC12IV__NONE: break; // Vector 0: No interrupt
case ADC12IV__ADC12OVIFG:
__no_operation();
break; // Vector 2: ADC12MEMx Overflow
case ADC12IV__ADC12TOVIFG:
__no_operation();
break; // Vector 4: Conversion time overflow
case ADC12IV__ADC12HIIFG: break; // Vector 6: ADC12BHI
case ADC12IV__ADC12LOIFG: break; // Vector 8: ADC12BLO
case ADC12IV__ADC12INIFG: break; // Vector 10: ADC12BIN
case ADC12IV__ADC12IFG0: // Vector 12: ADC12MEM0 Interrupt
break;
case ADC12IV__ADC12IFG1: break; // Vector 14: ADC12MEM1
case ADC12IV__ADC12IFG2: break; // Vector 16: ADC12MEM2
case ADC12IV__ADC12IFG3: break; // Vector 18: ADC12MEM3
case ADC12IV__ADC12IFG4: break; // Vector 20: ADC12MEM4
case ADC12IV__ADC12IFG5: break; // Vector 22: ADC12MEM5
case ADC12IV__ADC12IFG6: break; // Vector 24: ADC12MEM6
case ADC12IV__ADC12IFG7: break; // Vector 26: ADC12MEM7
case ADC12IV__ADC12IFG8: break; // Vector 28: ADC12MEM8
case ADC12IV__ADC12IFG9: break; // Vector 30: ADC12MEM9
case ADC12IV__ADC12IFG10: break; // Vector 32: ADC12MEM10
case ADC12IV__ADC12IFG11: break; // Vector 34: ADC12MEM11
case ADC12IV__ADC12IFG12: break; // Vector 36: ADC12MEM12
case ADC12IV__ADC12IFG13: break; // Vector 38: ADC12MEM13
case ADC12IV__ADC12IFG14: break; // Vector 40: ADC12MEM14
case ADC12IV__ADC12IFG15: break; // Vector 42: ADC12MEM15
case ADC12IV__ADC12IFG16: break; // Vector 44: ADC12MEM16
case ADC12IV__ADC12IFG17: break; // Vector 46: ADC12MEM17
case ADC12IV__ADC12IFG18: break; // Vector 48: ADC12MEM18
case ADC12IV__ADC12IFG19: break; // Vector 50: ADC12MEM19
case ADC12IV__ADC12IFG20: break; // Vector 52: ADC12MEM20
case ADC12IV__ADC12IFG21: break; // Vector 54: ADC12MEM21
case ADC12IV__ADC12IFG22: break; // Vector 56: ADC12MEM22
case ADC12IV__ADC12IFG23: break; // Vector 58: ADC12MEM23
case ADC12IV__ADC12IFG24: break; // Vector 60: ADC12MEM24
case ADC12IV__ADC12IFG25: break; // Vector 62: ADC12MEM25
case ADC12IV__ADC12IFG26: break; // Vector 64: ADC12MEM26
case ADC12IV__ADC12IFG27: break; // Vector 66: ADC12MEM27
case ADC12IV__ADC12IFG28: break; // Vector 68: ADC12MEM28
case ADC12IV__ADC12IFG29: break; // Vector 70: ADC12MEM29
case ADC12IV__ADC12IFG30: break; // Vector 72: ADC12MEM30
case ADC12IV__ADC12IFG31: break; // Vector 74: ADC12MEM31
case ADC12IV__ADC12RDYIFG: break; // Vector 76: ADC12RDY
default: break;
}
}
