各位先進大家好:
初涉MSP430系列，有許多地方看到datasheet仍然是懵懵懂懂，請各位見諒!
【芯片型号】MSP430F5338
【CCS版本】Code Composer Studio Version: 6.1.0.00104
【问题描述】我的開發板電源是參考以下圖去設計的
我遇到的問題是，當我要初始化讓第77隻腳(也是供給LCD的Vcc電源)，讓第77隻腳未能輸出3V，我該如何設定呢?我初始化以下的Code，怎麼設都只有輸出2.5V
是否有哪個環節出錯，還請各位先進指教，謝謝!
void main(void) {
// Stop watchdog timer to prevent time out reset 停止看門狗
WDTCTL = WDTPW + WDTHOLD;
sys_init();
sys_extpower_switch(true); //呼叫sys.c，如附件內容
while(1){
__delay_cycles(6000000ul);
}
}
void sys_init(void)
{
PMMCTL0_H = PMMPW_H; /* Open PMM Registers for write and set */
// Disable the GPIO power-on default high-impedance mode to activate
// previously configured port settings
PM5CTL0 &= ~LOCKLPM5 ; //PM5CTL0 = 0x00; /* reset LPM5LOCK bit (解鎖IO)*/
/* initialize all ports to reduce power consumption */
P4DIR = 0xff;
P4OUT = 0;
P3DIR = 0xff;
P3OUT = 0;
P2DIR = 0xff;
P2OUT = 0;
P1DIR = 0xfc;
P1OUT = 0x03;
P9DIR = 0xff;
P9OUT = 0;
P5DIR |= 0xfe;
P5OUT = 0;
P7DIR = 0xff;
P7OUT = 0;
/* enable port u output (used to switch power on the system) */
// Configure PU.0 as output pins
LDOKEYPID = 0x9628; /* Enable access to config registers,unlock LDO module */
//PUCTL = (1 << 5); /* enable, PU.0 and PU.1 are low*/
PUCTL |= PUOPE + PUOUT1; // PortU input enable
// PU.0 = low and PU.1 = high
LDOKEYPID = 0x0000; /* // Disbale access to config registers ,lock LDO module */
/* initialize clock to 12 MHz */
s_sys_init_clock();
}
void SetVCoreUp (unsigned int level)
{
// Open PMM registers for write access
PMMCTL0_H = 0xA5;
// Set SVS/SVM high side new level
SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
// Set SVM low side to new level
SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
// Wait till SVM is settled
while ((PMMIFG & SVSMLDLYIFG) == 0);
// Clear already set flags
PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
// Set VCore to new level
PMMCTL0_L = PMMCOREV0 * level;
// Wait till new level reached
if ((PMMIFG & SVMLIFG))
while ((PMMIFG & SVMLVLRIFG) == 0);
// Set SVS/SVM low side to new level
SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
// Lock PMM registers for write access
PMMCTL0_H = 0x00;
}
static void s_sys_init_clock(void)
{
/* Power settings */
SetVCoreUp(1u);
SetVCoreUp(2u);
SetVCoreUp(3u);
UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation
UCSCTL2 = FLLD_1 + 374; // Set DCO Multiplier for 12MHz
// (N + 1) * FLLRef = Fdco
// (374 + 1) * 32768 = 12MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle
__delay_cycles(375000);
// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}
while (SFRIFG1&OFIFG); // Test oscillator fault flag
}
void sys_extpower_switch(bool pwrOn)
{
LDOKEYPID = 0x9628; /* unlock LDO module */
if (pwrOn)
PUCTL |= (1 << 1) | (1 << 0);
else
{
PUCTL &= ~(1 << 5);
PUCTL &= ~((1 << 1) | (1 << 0));
//LDOPWRCTL = 0x0000;
}
LDOKEYPID = 0x0000; /* lock LDO module */
}
#pragma vector = PORT1_VECTOR
__interrupt void POWERUP_ISR(void)
{
__delay_cycles(12000ul*5ul); /* wait 500 ms */
__bic_SR_register_on_exit(LPM4_bits);
WDTCTL = WDTPW | WDTIS__64 | WDTCNTCL_L;
/* while(1)
{
__no_operation();
__no_operation();
__no_operation();
}*/
}
void sys_standby(void)
{
P4OUT = 0;
P4DIR = 0xff;
P3OUT = 0;
P3DIR = 0xff;
P2OUT = 0;
P2DIR = 0xff;
P1OUT = 0x03;
P1DIR = 0xfc;
P9OUT = 0;
P9DIR = 0xff;
P5DIR |= 0xfe;
P5OUT = 0;
P7DIR = 0xff;
P7OUT = 0;
/* power down lcd */
P8OUT = 0x00;
P6OUT = 0x00;
sys_extpower_switch(false);
__delay_cycles(12000000ul); /* wait 1 s*/
UCA1CTL1 = UCSWRST;
dac_stop_wave();
UCB1CTL0 = 0;
UCB1CTL1 = UCSWRST;
DAC12_0CTL0 = 0;
DAC12_0CTL0 = 0;
P1IES = 0x01;
P1IE = 0x01; /* enable P1.0 interrupt */
P1IFG = 0x00; /* clear interrupts */
UCSCTL8 = 0x00; /* disable clock requests*/
UCSCTL4 = (1 << 8) | (1 << 4) | (1 << 0); // all clock sources = VLO
UCSCTL6 = 0xC1CD; /* disable XT2 Oscillator */
PMMCTL0_H = PMMPW_H;
PMMCTL0_L |= PMMREGOFF;
__bis_SR_register(LPM4_bits + GIE);
__no_operation();
while(1);
}
