TIDM-02013: Research on the Synchronous Rectification Technology of the CLLLC Resonant Converter

Part Number: TIDM-02013
Other Parts Discussed in Thread: PMP22650

F0091TEK.BMP

The blue waveform represents the secondary - side current, while the others are the two - channel secondary - side driving signals. As shown in the figure, the synchronous rectification (SR) operation should be functioning properly. However, during the experiment, when the secondary - side driving was enabled, the input voltage rose sharply. Under this condition, the input voltage was set at 10 V with a connected load of 20 Ω, but the input current had already reached 3 A. Subsequently, when I replaced the load resistor with a 100 - Ω one, the input voltage and current remained unchanged. Therefore, it is likely that a short - circuit fault occurred in a certain part of the circuit. When the secondary - side driving was disabled and the secondary side operated temporarily as a diode bridge, both the input and output voltages and currents returned to normal levels.
 
In summary, the current fault is probably caused by a short circuit in a certain circuit triggered by the enabling of the secondary - side driving. (It should be specially noted that since a Rogowski coil of the same model could not be found, a Hall sensor was adopted as the current detection scheme instead, and the blue secondary - side current waveform shown is the signal processed by an operational amplifier.) At present, I consider the possible causes of this problem as follows: 1. The current detection scheme; 2. Insufficient driving delay between the primary and secondary sides; 3. Improper synchronous rectification thresholds (set at 2100 and 2000) and insufficient blanking time.
 
Your reply would be highly appreciated, as this issue is of great importance to me. Thank you.
  • Hello, we have received your case and the investigation will take some time. Thank you for your patience.

  • As previously mentioned, for the Rogowski coil in the original design, the detected current is inverse to the actual value; after passing through the operational amplifier, it becomes in-phase with the actual value, thus providing correct sampling data for the DSP.
    However, the Hall sensor I am currently using outputs a detected current that is consistent with the actual value. After going through the operational amplifier, the signal becomes out-of-phase with the actual value. This causes the driving signal to be completely opposite to the required one, resulting in a secondary-side short circuit and generating an excessive current.
  • I tried swapping the current input and output terminals of the Hall sensor, yet this did not resolve the short-circuit issue in the secondary-side circuit. I then measured the gate drives of the primary-side 2L bridge and secondary-side 2L bridge, and observed that the two drive signals—which should have been in phase—now had a phase difference of 180°. This is likely the root cause of the short circuit. The problem should lie in an incorrect reference of the drive signals for the secondary-side bridge arm, but I have no idea where to modify the settings.I recall that the code describes the secondary-side drive being referenced to the primary side, yet I cannot locate the function where this reference is configured. Could you please advise me on this? 

    The blue line represents the sampled current after the operational amplifier, the purple line represents the driving waveform of the primary-side 2L after the isolation chip, and the yellow line represents the driving waveform of the secondary-side 2L before the isolation chip.

    I apologize for troubling you so frequently. This experiment is of great importance to me, and I truly appreciate you taking the time to answer my questions.

  • For 02013, the transformer polarity is positive, so the macro CLLLC_TRANSFORMER_POLARITY should be set to CLLLC_POSITIVE_POLARITY.

    #if CLLLC_TRANSFORMER_POLARITY == CLLLC_POSITIVE_POLARITY
    //The following code should be used when the transformer polarity matches the schematic.
    EPWM_setTripZoneAdvAction(CLLLC_SEC_LEG1_PWM_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZA_D, EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAdvAction(CLLLC_SEC_LEG1_PWM_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZA_U, EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAdvAction(CLLLC_SEC_LEG1_PWM_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZB_D, EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAdvAction(CLLLC_SEC_LEG1_PWM_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZB_U, EPWM_TZ_ADV_ACTION_LOW);

    EPWM_setTripZoneAdvAction(CLLLC_SEC_LEG2_PWM_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZA_D, EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAdvAction(CLLLC_SEC_LEG2_PWM_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZA_U, EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAdvAction(CLLLC_SEC_LEG2_PWM_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZB_D, EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAdvAction(CLLLC_SEC_LEG2_PWM_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZB_U, EPWM_TZ_ADV_ACTION_LOW);
    #else
    //The following code should be used when the transformer polarity does not match the schematic.
    EPWM_setTripZoneAdvAction(CLLLC_SEC_LEG1_PWM_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZA_U, EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAdvAction(CLLLC_SEC_LEG1_PWM_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZA_D, EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAdvAction(CLLLC_SEC_LEG1_PWM_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZB_U, EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAdvAction(CLLLC_SEC_LEG1_PWM_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZB_D, EPWM_TZ_ADV_ACTION_LOW);

    EPWM_setTripZoneAdvAction(CLLLC_SEC_LEG2_PWM_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZA_U, EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAdvAction(CLLLC_SEC_LEG2_PWM_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZA_D, EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAdvAction(CLLLC_SEC_LEG2_PWM_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZB_U, EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAdvAction(CLLLC_SEC_LEG2_PWM_BASE, EPWM_TZ_ADV_ACTION_EVENT_TZB_D, EPWM_TZ_ADV_ACTION_LOW);
    #endif

    In clllc_user_setting.h

    #define CLLLC_TRANSFORMER_POLARITY CLLLC_NEGATIVE_POLARITY

  • Hi,

    May I know what HW is used here. Is it PMP22650 or any change to that?

  • I tried the method mentioned above: when I reversed the transformer's polarity, the secondary side didn't short-circuit, but the synchronous rectification also stopped working. Only when the polarity was set to negative did the synchronous rectification operate normally.
    So I swapped pins 3 and 4 on the transformer's secondary side, making pins 1L and 8L in-phase. This adjustment allowed the CLLLC converter to achieve proper synchronous rectification.
    If anyone attempts to replicate this experiment later, this can serve as a reference. Sorry for the bother.