void ADC0SS2_IRQHandler(void)
{
uint32_t getIntStatus;
/* Get the interrupt status from the ADC */
getIntStatus = MAP_ADCIntStatusEx(ADC0_BASE, true);
/* If the interrupt status for Sequencer-2 is set the
* clear the status and read the data */
if((getIntStatus & ADC_INT_DMA_SS2) == ADC_INT_DMA_SS2)
{
/* Clear the ADC interrupt flag. */
MAP_ADCIntClearEx(ADC0_BASE, ADC_INT_DMA_SS2);
/* Reconfigure the channel control structure and enable the channel */
MAP_uDMAChannelTransferSet(UDMA_CH16_ADC0_2 | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
(void *)&ADC0->SSFIFO2, (void *)&srcBuffer,
sizeof(srcBuffer)/2);
MAP_uDMAChannelEnable(UDMA_CH16_ADC0_2);
/* Set conversion flag to true */
bgetConvStatus = true;
}
}
void ConfigureUART(uint32_t systemClock)
{
/* Enable the clock to GPIO port A and UART 0 */
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
/* Configure the GPIO Port A for UART 0 */
MAP_GPIOPinConfigure(GPIO_PA0_U0RX);
MAP_GPIOPinConfigure(GPIO_PA1_U0TX);
MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
/* Configure the UART for 115200 bps 8-N-1 format */
UARTStdioConfig(0, 115200, systemClock);
}
int main(void)
{
uint32_t systemClock;
uint32_t i=0;
/* Configure the system clock for 120 MHz */
systemClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN |
SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480),
120000000);
/* Initialize serial console */
ConfigureUART(systemClock);
/* Enable the clock to GPIO Port E and wait for it to be ready */
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
while(!(MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOE)))
{
}
/* Configure PE0-PE3 as ADC input channel */
MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_3);
MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_2);
MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_1);
MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_0);
/* Enable the clock to ADC-0 and wait for it to be ready */
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
while(!(MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_ADC0)))
{
}
/* Configure Sequencer 2 to sample the analog channel : AIN0-AIN3. The
* end of conversion and interrupt generation is set for AIN3 */
MAP_ADCSequenceStepConfigure(ADC0_BASE, 2, 0, ADC_CTL_CH3 | ADC_CTL_IE |
ADC_CTL_END);
/* Enable sample sequence 2 with a timer signal trigger. Sequencer 2
* will do a single sample when the timer generates a trigger on timeout*/
MAP_ADCSequenceConfigure(ADC0_BASE, 2, ADC_TRIGGER_TIMER, 2);
ADC0->CC=0x0;
/* Clear the interrupt status flag before enabling. This is done to make
* sure the interrupt flag is cleared before we sample. */
MAP_ADCIntClearEx(ADC0_BASE, ADC_INT_DMA_SS2);
MAP_ADCIntEnableEx(ADC0_BASE, ADC_INT_DMA_SS2);
/* Enable the DMA request from ADC0 Sequencer 2 */
MAP_ADCSequenceDMAEnable(ADC0_BASE, 2);
/* Since sample sequence 2 is now configured, it must be enabled. */
MAP_ADCSequenceEnable(ADC0_BASE, 2);
/* Enable the Interrupt generation from the ADC-0 Sequencer */
MAP_IntEnable(INT_ADC0SS2);
/* Enable the DMA and Configure Channel for TIMER0A for Ping Pong mode of
* transfer */
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
while(!(SysCtlPeripheralReady(SYSCTL_PERIPH_UDMA)))
{
}
MAP_uDMAEnable();
/* Point at the control table to use for channel control structures. */
MAP_uDMAControlBaseSet(pui8ControlTable);
/* Map the ADC0 Sequencer 2 DMA channel */
MAP_uDMAChannelAssign(UDMA_CH16_ADC0_2);
/* Put the attributes in a known state for the uDMA ADC0 Sequencer 2
* channel. These should already be disabled by default. */
MAP_uDMAChannelAttributeDisable(UDMA_CH16_ADC0_2,
UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST |
UDMA_ATTR_HIGH_PRIORITY |
UDMA_ATTR_REQMASK);
/* Configure the control parameters for the primary control structure for
* the ADC0 Sequencer 2 channel. The primary control structure is used for
* copying the data from ADC0 Sequencer 2 FIFO to srcBuffer. The transfer
* data size is 16 bits and the source address is not incremented while
* the destination address is incremented at 16-bit boundary.
*/
MAP_uDMAChannelControlSet(UDMA_CH16_ADC0_2 | UDMA_PRI_SELECT,
UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 |
UDMA_ARB_4);
/* Set up the transfer parameters for the ADC0 Sequencer 2 primary control
* structure. The mode is Basic mode so it will run to completion. */
MAP_uDMAChannelTransferSet(UDMA_CH16_ADC0_2 | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
(void *)&ADC0->SSFIFO2, (void *)&srcBuffer,
sizeof(srcBuffer)/4);
/* The uDMA ADC0 Sequencer 2 channel is primed to start a transfer. As
* soon as the channel is enabled and the Timer will issue an ADC trigger,
* the ADC will perform the conversion and send a DMA Request. The data
* transfers will begin. */
MAP_uDMAChannelEnable(UDMA_CH16_ADC0_2);
/* Enable Timer-0 clock and configure the timer in periodic mode with
* a frequency of 1 KHz. Enable the ADC trigger generation from the
* timer-0. */
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);
while(!(MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_TIMER0)))
{
}
MAP_TimerConfigure(TIMER0_BASE, TIMER_CFG_A_PERIODIC_UP);
MAP_TimerLoadSet(TIMER0_BASE, TIMER_A, (systemClock/10000));
MAP_TimerADCEventSet(TIMER0_BASE, TIMER_ADC_TIMEOUT_A);
MAP_TimerControlTrigger(TIMER0_BASE, TIMER_A, true);
MAP_TimerEnable(TIMER0_BASE, TIMER_A);
/* Wait loop */
while(1)
{
/* Wait for the conversion to complete */
while(!bgetConvStatus);
bgetConvStatus = false;
/* Display the AIN0-AIN03 (PE3-PE0) digital value on the console. */
for(i=0;i<1024;++i){
UARTprintf("%d:%d\n",i,srcBuffer[i]);
}
MAP_SysCtlDelay(systemClock / 4);
}
}
代码是在adc timertrigger dma例程基础上修改的
其中添加了ADC0->CC=0x0;语句 将adc0的采样来源改为pll （32m）为了达到2m采样率
但是采样出来的数据非常奇怪 采集gnd的数据为1023 采集3.3v的数据为2806
想知道除了修改adc0的寄存器还需要改动哪里才能获得2m的采样率
