URGENT: Why My Parallel MOSFETs Keep Failing Due to Current Imbalance? Help Me Fix This!

1. Key Symptoms & Test Data

• Setup:
   Full-bridge configuration, 150kHz switching
   Gate drive: TI UCC21520 with 4.7Ω series resistors
   Source resistors: 10mΩ/2W, connected to TI INA240 current monitor
• Abnormal findings:
  ️ Device #1 & #3 show 18A/12A current split at 60A total
  ️ Junction temp difference: 25°C between hottest/coldest MOSFET
  ️ Scope shows 50ns switching delay mismatch between devices

2. Potential Causes (Need Your Input!)

2.1 Component Matching Issues

• Question: Did I skip critical screening?
  • Used random batch MOSFETs (Vth spread: 2.8V-3.5V)
  • Rds(on) at 25°C: 75mΩ-82mΩ (data sheet says 75mΩ±10%)
  • TI Expert tip: Should I use TI's parametric binning service for TMOS devices?

2.2 Layout Parasitics

• My PCB design:
  ️ 4-layer board, but source traces vary by 2mm length
  ️ Gate drive tracks routed on different layers (FR4 dielectric)
  • Community challenge: How to model source inductance in PSpice? (Using TI's TINA-TI but no luck)

2.3 Thermal Runaway Mechanism

• Observed cycle:
  1. Device #1 carries more current → heats up
  2. Rds(on) increases 0.5%/°C → but current shifts to device #3
  3. Device #3 now overheats, repeats...
  • Technical question: Does TI's LM5146 current-share controller handle dynamic thermal effects?

3. What I’ve Tried (Failed Solutions)

 Added 220pF snubber caps across D-S (no change)
 Tried active current balancing with TI CSD88599Q5DC (still imbalanced)
 Swapped to Kelvin-source TO-247-4L MOSFETs (improvement but not solved)

4. Desperate for Your Design Tricks!

• Specific help needed:
  1. Best practices for paralleling MOSFETs in TI reference designs?
  2. How to implement real-time current sharing with MCU (using TM4C129)?
  3. Recommended TI parts for high-reliability paralleling (drivers/sensors)?

5. Bonus: My SPICE Model & Layout Screenshot

• Note: Thermal simulation shows hotspots at source via connections—could via inductance be the culprit?