UCC256404: UCC256404: Simulation issues with UCC256404 and UCC28056

Part Number: UCC256404
Other Parts Discussed in Thread: UCC24624, UCC28056

Dear TI Technical Support Team,

Hello! I am currently designing a half-bridge LLC resonant converter using the UCC256404B controller, the UCC28056B PFC controller, and the UCC24624 synchronous rectifier driver. During simulation and design, I have encountered several critical issues and would greatly appreciate your professional guidance.

First, regarding MOSFET current and voltage spikes at startup: In simulation, when using MOSFET models, I observed large current and voltage spikes on the primary-side MOSFETs at the moment of startup. Adding a small amount of parasitic inductance does not eliminate these spikes. After reviewing relevant materials, I suspect the issue is caused by the MOSFETs' initial parasitic capacitance being zero and hard switching. Is there a solution for this?

Second, regarding soft start and output voltage overshoot: I am facing a dilemma with the soft start implementation. Increasing the soft start capacitor value to slow down the voltage ramp‑up causes severe output voltage overshoot. Adjusting the feedback loop parameters to suppress the overshoot then introduces loop stability problems. Is there a way to solve both issues simultaneously?

Third, regarding the UCC28056 startup issue: Sometimes, due to a small voltage difference during startup, the UCC28056 enters CCM mode, which creates an inductor current spike. How can this problem be resolved?

Fourth, regarding integrated simulation of multi‑controller designs: My design uses three separate ICs (UCC256404B, UCC28056B, UCC24624), each with its own simulation model. I would like to simulate the complete system in the same environment to verify end‑to‑end performance. Is it possible to place the three model files into the same project? If so, how should I do it?

Thank you for your time and support. I look forward to your reply.   

  • Hello, we have received your case and the investigation will take some time. Thank you for your patience.

  • 你好,

    增加 SS 电容或许可以减少启动时的电流尖峰。关于第二个问题,确实需要在减缓 SS 电压斜坡和 Vout 过冲之间进行权衡,但正如您所说,调整补偿参数以加快环路响应速度可以缓解这个问题。数据手册中提到了 SS 电容的最大值和最小值,只要您的环路响应速度不太慢,就不会产生明显的过冲。PFC 在启动期间进入 CCM 模式,能否提供 VDS、VBLK 和 VZCD 的放大波形?请同时提供高电平和低电平两种情况的波形图。TI方面尚未验证在单个 SIMPLIS 仿真中同时使用 UCC256404B、UCC28056B 和 UCC24624 是否可行。

    问候,

    普里坦