TPS546E25-DESIGN: TPS546E25: Does the Official SIMPLIS Model Support Multiphase Stacking and Phase Interleaving?

Part Number: TPS546E25-DESIGN
Other Parts Discussed in Thread: TPS546C25, TPS546E25

Hello TI Support Team,

I am using the official TPS546C25/TPS546E25 SIMPLIS model (SLVMEC4) from the TI product page to build a multiphase TPS546E25 converter.

My final target is a 4-phase interleaved TPS546E25 converter, with each phase operating at approximately 800 kHz. According to the TPS546E25 datasheet and the application brief “Achieving Higher Output Current by Stacking TPS546E25 and TPS546C25 DC/DC Converters”, the devices should be able to operate as a stacked multiphase converter using the TRIGGER and ISHARE connections, with the secondary phases switching out of phase with the primary.

To simplify troubleshooting, I first reduced the circuit to a 2-phase configuration using two instances of the official SIMPLIS model.

The primary and secondary pin-strap settings are configured according to the datasheet:

Primary U4:
MSEL1 = 2.74 kΩ
MSEL2 = 11.3 kΩ
PMB_ADDR/VORST# = 26.7 kΩ
VSEL/FB = 11.3 kΩ

Secondary U5:
MSEL1 = 1 MΩ (>412 kΩ, Secondary)
MSEL2 = 7.32 kΩ
PMB_ADDR/VORST# = 2.21 kΩ
VSEL/FB = 11.3 kΩ

Therefore, the PMB_ADDR configuration corresponds to a 2-phase stack with Common Address 0Eh, with U5 configured as the first secondary device.

The TRIGGER pins are connected together, the ISHARE pins are connected together, both devices share the same CNTL signal, and the VOSNS/GOSNS connections are also connected to the common output sensing point.

However, in the transient simulation, I observe that SW1 and SW2 switch at essentially the same time. Their rising and falling edges overlap, and no approximately 180-degree phase displacement is observed.

At 800 kHz, I would expect the nominal phase separation of a 2-phase system to be approximately 625 ns. In my simulation, this phase separation does not occur.

Interestingly, the attached waveform also shows activity on the common TRIGGER node, but the secondary SW waveform still remains aligned with the primary SW waveform.

When I extend the same approach to four TPS546E25 models, the four phase currents are also effectively in phase. Therefore, the inductor current ripple from each phase adds together instead of obtaining the expected ripple cancellation from 90-degree interleaving.

I have attached:

1. The modified SIMPLIS schematic (.sxsch);
2. The waveform file / screenshot showing TRIGGER_TEST, SW1_TEST, and SW2_TEST;
3. The two-phase circuit used for troubleshooting.

Could you please help confirm the following?

Does the official TPS546E25 SIMPLIS model SLVMEC4 support the actual multiphase stacking / phase-interleaving behavior through the TRIGGER and ISHARE pins?

If the model does support multiphase interleaving, could you please advise whether any additional model configuration, simulation setting, PMBus setting, or connection is required to enable the phase shifting?

If this function is not implemented in the current SIMPLIS macro-model, is there a TI-supported 2-phase or 4-phase SIMPLIS model/reference schematic that can correctly simulate the interleaved switching behavior and phase-current ripple cancellation?TPS546x25_STARTUP_Loop_Response_double_P.pdf 

I have attached my SIMPLIS schematic so that the configuration can be checked directly.

Thank you very much for your help.

Best regards