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TDA4VH-Q1: The actual usage status of PCIe is inconsistent with the display shown by the software.

JiaJing Hu
Prodigy 20 points
Part Number: TDA4VH-Q1

Hi,Ti

During the debugging of a PCIe device, we encountered an issue where the actual configuration is PCIe Gen3 x2 Lane. The software should display "8GT/s Width x2," but it currently shows "2.5GT/s Width x4." We would like to inquire about the possible conditions that could lead to this discrepancy.

The diagram below shows the SSD schematic configuration

The following figure displays the software log output

  • 0
    TI__Mastermind 30280 points

    Hello!

    We have received your case and will take some time. Thank you for your patience.

  • 0
    TI__Mastermind 30280 points

    PCIe will try to negotiate to the fastest speed and widest lane number that both the EP and RC side support.

    Width being overdriven to x4 despite LnkCap reporting Width x1 is strange, but speed being 2.5GT/s can be due to a couple of issues.

    1. The EP that is connected to the PCIe slot of TDA4VH only supports 2.5GT/s
    2. There were issues in link training. If the EP supports 8.0GT/s or faster, and if there are issues during the link equalization phase of LTSSM, then PCIe will only negotiate to 2.5GT/s.
      1. If as an experiment, the speed is limited to 5.0GT/s through TDA4VH software or EP hardware/software, and PCIe negotiates up to 5.0GT/s, then most likely there are issues during the link equalization phase, since 5.0GT/s and 2.5GT/s are both speeds that do not require link equalization.

    So please try to check if EP side supports speeds faster than 2.5GT/s, and if yes, please try experimenting with speed and see if 5.0GT/s can link up.