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WDEL Enable the delay counter at the end of the current transaction. Note: The WDEL bit is supported in master mode only. In slave mode, this bit will be ignored.
0 No delay will be inserted. However, SPIx_SCS[1:0] pins will still be de-activated for at least for two SPI peripheral clock cycles if CSHOLD = 0. Note: In SPI, the duration for which the SPIx_SCS[1:0] pins remaining de-activated will also depend upon time taken to supply a new data after completing the shifting operation. If the internal buffer TXBUF is already full, then the SPIx_SCS[1:0] pins will be de-asserted for at least two SPI peripheral clock cycles (if WDEL = 0).
1 After a transaction, WDELAY of the corresponding data format will be loaded into the delay counter. No transaction will be performed until the WDELAY counter overflows. The SPIx_SCS pins will be de-activated for at least (WDELAY + 2) SPI peripheral clock_Period duration.
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