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Description Causes an internal exception to be taken. It can be used as a mechanism for User mode programs to request Supervisor mode services. Execution of the SWE instruction results in an exception being recognized in the E1 pipeline phase containing the SWE instruction. The SXF bit in EFR is set to 1. The HWE bit in NTSR is cleared to 0. If exceptions have been globally enabled, this causes an exception to be recognized before execution of the next execute packet. The address of that next execute packet is placed in NRP.
SWENR:
Description Causes an internal exception to be taken. It is intended for use in systems supporting a secure operating mode. It can be used as a mechanism for User mode programs to request Supervisor mode services. It differs from the SWE instruction in four ways: 1. TSR is not copied into NTSR. 2. No return address is placed in NRP (it remains unmodified). 3. The IB bit in TSR is set to 1. This will be observable only in the case where another exception is recognized simultaneously. 4. A branch to REP (restricted entry point register) is forced in the context switch rather than the ISTP-based exception (NMI) vector. This instruction executes unconditionally. If another exception (internal or external) is recognized simultaneously with the SWENR-raised exception then the other exception(s) takes priority and normal exception behavior occurs; that is, NTSR and NRP are used and execution is directed to the NMI vector.
