If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
18.2.5.6.8 Interfacing to a Non-CE Don't Care NAND Flash As explained in Section 18.2.5.6.4, the EMIFA does not support NAND Flash devices that require the chip select signal to remain low during the tR time for a read. One way to work around this limitation is to use a GPIO pin to drive the CE signal of the NAND Flash device. If this work around is implemented, software will configure the selected GPIO to be low, then begin the NAND Flash operation, starting with the command phase. Once the NAND Flash operation has completed the software can then configure the selected GPIO to be high.
