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如何操作6748 UPP_D3当GPIO输出



误以为UPP_D3引脚(编号153)可以配置为普通GPIO使用,实际上6748只有141个GPIO,将UPP_D3,UPP_D4,SPI1_CLK作为了FPGA的配置电路,需要用这三个引脚产生一个配置时序,但UPP的数据引脚并不能当成普通GPIO使用,电路已经设计好,还有没有补救办法?