2.2.3 Local Reset
In addition to module reset described in the previous section, the C66x core can be reset using a special
local reset. When local reset is asserted, the internal memories (L1P, L1D, and L2) for the core are still
accessible. The local reset resets only the corresponding C66x core, not the rest of the chip. Local reset is
intended to be used by the watchdog timers to reset the C66x core in the event of an error. The
procedures for asserting and de-asserting local reset are as follows (Y denotes the module domain
number):
1. Set MDCTL[Y].LRSTZ to 0x0 to assert local reset.
2. Set MDCTL[Y].LRSTZ to 0x1 to de-assert local reset. The C66x core immediately executes program
instructions after reset is de-asserted. Note that the boot sequence does not re-occur unless there is a
device-level reset. Execution of code previously in L2 begins execution.
红字的这部分，究竟是解复位阻止了C66x core在复位之后立刻执行指令，还是说C66x core在复位之后，立刻执行指令是被解能了，必须由解复位使能后，才可以允许C66x core执行指令？
问题二，在local reset之后，按照文档，C66x core应该是从L2的最后一个字处获取入口地址，那么如果我在local reset之前将新的入口地址填入，是否能在local reset之后触发C66x core从新的入口地址执行指令？是否我还需要在de-assert之后再向C66 core发送一个IPC中断？
问题三，在核0local reset之后是否会影响pll？pll是否还保持local reset之前的配置？因为我看到《TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor Data Manual》Table 7-7 Clock Domains中，pll controller是不参与LPSC的。
我参考了ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\pcieboot_localreset\src\pcieboot_localreset.c
和
ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\linux_host_loader\pciedemo.c
中的代码，前者的方法很巧妙但是无法触发，后者我看到都是需要在assert之后de-assert的，但是没有发ipc中断。
