开发平台为EVM5515，由于PC28F128P30T85已经停产，且价格很高，120RMB/PCS。
PC28F128P30T85和MT28GU256AAA2EGC是Pin to Pin兼容的，容量分别是128MB和256MB。
如果将PC28F128P30T85换成MT28GU256AAA2EGC后，驱动参数怎么修改？
EVM5515开发板的例程CSL_EMIF_NOR_CpuTransfer文件如下
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2008
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** @file csl_nor.c
*
* @brief NOR functional layer API source file
*
* Path: \(CSLPATH)\src\nor\src
*/
/* ============================================================================
* Revision History
* ================
* 15-Oct-2010 Created
* ============================================================================
*/
#include "..\inc\csl_nor.h"
CSL_Status NOR_setup(CSL_NorObj *norObj, Uint16 instId)
{
CSL_Status status;
status = CSL_SOK;
norObj->emifRegs = CSL_EMIF_REGS;
norObj->sysCtrlRegs = CSL_SYSCTRL_REGS;
norObj->instId = instId;
return status;
}
CSL_Status NOR_emifResetAndClock(CSL_NorHandle hNor)
{
CSL_Status status;
Uint16 i;
status = CSL_SOK;
/* Configure EMIF */
/* 1c26h ECDR */
CSL_FINS(hNor->sysCtrlRegs->ECDR, SYS_ECDR_EDIV, 0x1);
/* 1c04h PSRCR - Set Reset Count */
CSL_FINS(hNor->sysCtrlRegs->PSRCR, SYS_PSRCR_COUNT, 0x20);
/* 1c05h PRCR - enable emif self-clearing*/
CSL_FINS(hNor->sysCtrlRegs->PRCR, SYS_PRCR_PG4_RST, 0x0);
/* 1c05h PRCR - Reset EMIF */
CSL_FINS(hNor->sysCtrlRegs->PRCR, SYS_PRCR_PG1_RST, 0x1);
/* Give some delay for the device to reset */
for(i = 0; i < 100; i++){;}
/* Enable EMIF module in Idle PCGCR */
CSL_FINST(hNor->sysCtrlRegs->PCGCR1, SYS_PCGCR1_EMIFCG, ACTIVE);
return status;
}
CSL_Status NOR_setupEmifChipSelect(CSL_NorHandle hNor, CSL_NorConfig *norCfg)
{
CSL_Status status;
volatile ioport Uint16 *asyncCSnCR1Addr;
volatile ioport Uint16 *asyncCSnCR2Addr;
status = CSL_SOK;
hNor->commandSet = norCfg->commandSet;
hNor->norWidth = norCfg->norWidth;
if(CSL_NOR_16_BIT == norCfg->norWidth) {
/*hNor->blockSize is in bytes. In 16bit device, one address points to 16bit or 2byte*/
hNor->blockLength = norCfg->blockSize/2;
} else if(CSL_NOR_8_BIT == norCfg->norWidth) {
hNor->blockLength = norCfg->blockSize;
}
hNor->numOfBlocks = norCfg->numOfBlocks;
hNor->writeBufferSize = norCfg->writeBufferSize;
hNor->norOpMode = norCfg->norOpMode;
hNor->enableUnlockSeq = TRUE;
/* hNor->intrNumNor = 0;
hNor->addrCycles = 0;*/
/* 1c00h EBSR - Configure EM_A[20:15] for EMIF */
CSL_FINS(hNor->sysCtrlRegs->EBSR, SYS_EBSR_A20_MODE, 0x0);
CSL_FINS(hNor->sysCtrlRegs->EBSR, SYS_EBSR_A19_MODE, 0x0);
CSL_FINS(hNor->sysCtrlRegs->EBSR, SYS_EBSR_A18_MODE, 0x0);
CSL_FINS(hNor->sysCtrlRegs->EBSR, SYS_EBSR_A17_MODE, 0x0);
CSL_FINS(hNor->sysCtrlRegs->EBSR, SYS_EBSR_A16_MODE, 0x0);
CSL_FINS(hNor->sysCtrlRegs->EBSR, SYS_EBSR_A15_MODE, 0x0);
/* 1c33h ESCR - EMIF generates 16bit access to External Memory for every word access */
CSL_FINS(hNor->sysCtrlRegs->ESCR, SYS_ESCR_BYTEMODE, 0x0);
/* 1004h AWCCR1 MEWC - 0xFF (max) */
CSL_FINS(hNor->emifRegs->AWCCR1, EMIF_AWCCR1_MEWC, norCfg->asyncWaitCfg->waitCycles);
switch(norCfg->norChipSelect)
{
case CSL_NOR_CS2:
/* 1005h AWCCR2 - EM_WAIT0 pin for EM_CS2 */
CSL_FINS(hNor->emifRegs->AWCCR2, EMIF_AWCCR2_CS2_WAIT, norCfg->asyncWaitCfg->waitPin);
hNor->CSnBASE = (Uint32)CSL_EMIF_CS2_DATA_BASE_ADDR;
hNor->DMABYTEADDR = (Uint32)CSL_NAND_CE0_ADDR;
asyncCSnCR1Addr = &hNor->emifRegs->ACS2CR1;
asyncCSnCR2Addr = &hNor->emifRegs->ACS2CR2;
break;
case CSL_NOR_CS3:
/* 1005h AWCCR2 - EM_WAIT0 pin for EM_CS3 */
CSL_FINS(hNor->emifRegs->AWCCR2, EMIF_AWCCR2_CS3_WAIT, norCfg->asyncWaitCfg->waitPin);
hNor->CSnBASE = (Uint32)CSL_EMIF_CS3_DATA_BASE_ADDR;
hNor->DMABYTEADDR = (Uint32)CSL_NAND_CE1_ADDR;
asyncCSnCR1Addr = &hNor->emifRegs->ACS3CR1;
asyncCSnCR2Addr = &hNor->emifRegs->ACS3CR2;
break;
case CSL_NOR_CS4:
/* 1005h AWCCR2 - EM_WAIT0 pin for EM_CS4 */
CSL_FINS(hNor->emifRegs->AWCCR2, EMIF_AWCCR2_CS4_WAIT, norCfg->asyncWaitCfg->waitPin);
hNor->CSnBASE = (Uint32)CSL_EMIF_CS4_DATA_BASE_ADDR;
hNor->DMABYTEADDR = (Uint32)CSL_ASYNC_CE0_ADDR;
asyncCSnCR1Addr = &hNor->emifRegs->ACS4CR1;
asyncCSnCR2Addr = &hNor->emifRegs->ACS4CR2;
break;
case CSL_NOR_CS5:
/* 1005h AWCCR2 - EM_WAIT0 pin for EM_CS5 */
CSL_FINS(hNor->emifRegs->AWCCR2, EMIF_AWCCR2_CS5_WAIT, norCfg->asyncWaitCfg->waitPin);
hNor->CSnBASE = (Uint32)CSL_EMIF_CS5_DATA_BASE_ADDR;
hNor->DMABYTEADDR = (Uint32)CSL_ASYNC_CE1_ADDR;
asyncCSnCR1Addr = &hNor->emifRegs->ACS5CR1;
asyncCSnCR2Addr = &hNor->emifRegs->ACS5CR2;
break;
default:
break;
}
switch(norCfg->asyncWaitCfg->waitPin)
{
case CSL_NOR_WAIT0:
/* 1005h AWCCR2 - Insert wait cycles if EM_WAIT0 is high/low */
CSL_FINS(hNor->emifRegs->AWCCR2, EMIF_AWCCR2_WP0, norCfg->asyncWaitCfg->waitPol);
break;
case CSL_NOR_WAIT1:
/* 1005h AWCCR2 - Insert wait cycles if EM_WAIT1 is high/low */
CSL_FINS(hNor->emifRegs->AWCCR2, EMIF_AWCCR2_WP1, norCfg->asyncWaitCfg->waitPol);
break;
case CSL_NOR_WAIT2:
/* 1005h AWCCR2 - Insert wait cycles if EM_WAIT2 is high/low */
CSL_FINS(hNor->emifRegs->AWCCR2, EMIF_AWCCR2_WP2, norCfg->asyncWaitCfg->waitPol);
break;
case CSL_NOR_WAIT3:
/* 1005h AWCCR2 - Insert wait cycles if EM_WAIT3 is high/low */
CSL_FINS(hNor->emifRegs->AWCCR2, EMIF_AWCCR2_WP3, norCfg->asyncWaitCfg->waitPol);
break;
default:
break;
}
/* 1010h ACS2CR1 */
CSL_FINS(*asyncCSnCR1Addr, EMIF_ACS2CR1_RSETUPLSB, (Uint16)(norCfg->asyncCfg->r_setup & 0x7));
/* Set read strobe duration cycles */
CSL_FINS(*asyncCSnCR1Addr, EMIF_ACS2CR1_RSTROBE, norCfg->asyncCfg->r_strobe);
/* Set read strobe hold cycles */
CSL_FINS(*asyncCSnCR1Addr, EMIF_ACS2CR1_RHOLD, norCfg->asyncCfg->r_hold);
/* Set turn around cycles */
CSL_FINS(*asyncCSnCR1Addr, EMIF_ACS2CR1_TA, norCfg->asyncCfg->turnAround);
/* Set asynchronous memory size */
CSL_FINS(*asyncCSnCR1Addr, EMIF_ACS2CR1_ASIZE, norCfg->asyncCfg->aSize);
/* 1011h ACS2CR2 */
CSL_FINS(*asyncCSnCR2Addr, EMIF_ACS2CR2_SS, norCfg->asyncCfg->selectStrobe);
/* Set extended wait mode bit */
CSL_FINS(*asyncCSnCR2Addr, EMIF_ACS2CR2_EW, norCfg->asyncCfg->ewMode);
/* Set write srobe setup cycles */
CSL_FINS(*asyncCSnCR2Addr, EMIF_ACS2CR2_WSETUP, norCfg->asyncCfg->w_setup);
/* Set write duration cycles */
CSL_FINS(*asyncCSnCR2Addr, EMIF_ACS2CR2_WSTROBE, norCfg->asyncCfg->w_strobe);
/* Set write hold cycles */
CSL_FINS(*asyncCSnCR2Addr, EMIF_ACS2CR2_WHOLD, norCfg->asyncCfg->w_hold);
/* Set read strobe setup cycles */
CSL_FINS(*asyncCSnCR2Addr, EMIF_ACS2CR2_RSETUPMSB, (norCfg->asyncCfg->r_setup >> 0x3));
#if 0
/* 1068h PGMODECTRL1 & 1069h PGMODECTRL2*/
/*For PHOENIX_QT*/
CSL_FINS(hNor->emifRegs->PAGEMODCTRL1, EMIF_PAGEMODCTRL1_CS2_PAGE_DELAY, 0x2);
CSL_FINS(hNor->emifRegs->PAGEMODCTRL1, EMIF_PAGEMODCTRL1_CS2_PAGE_SIZE, 0x1);
CSL_FINS(hNor->emifRegs->PAGEMODCTRL1, EMIF_PAGEMODCTRL1_CS2_PAGEMOD_EN, 0x1);
/*For EVM5515*/
CSL_FINS(hNor->emifRegs->PAGEMODCTRL1, EMIF_PAGEMODCTRL1_CS2_PAGE_DELAY, 0x2);
CSL_FINS(hNor->emifRegs->PAGEMODCTRL1, EMIF_PAGEMODCTRL1_CS2_PAGE_SIZE, 0x0);/*don't know*/
CSL_FINS(hNor->emifRegs->PAGEMODCTRL1, EMIF_PAGEMODCTRL1_CS2_PAGEMOD_EN, 0x0);/*don't know*/
#endif
return status;
}
CSL_Status NOR_readId(CSL_NorHandle hNor)
{
CSL_Status status;
status = CSL_SOK;
/* Read NOR ID */
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
*(CSL_VUint16*)hNor->CSnBASE = 0x90;
}
else if (CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
if(CSL_NOR_8_BIT == hNor->norWidth)
{
*(CSL_VUint16*)(hNor->CSnBASE+0xAAA) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0x55;
*(CSL_VUint16*)(hNor->CSnBASE+0xAAA) = 0x90;
}
else if(CSL_NOR_16_BIT == hNor->norWidth)
{
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+0x2AA) = 0x55;
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0x90;
}
}
__asm(" NOP");/*For "A write followed by A read" pre-fetch reordering*/
__asm(" NOP");
__asm(" NOP");
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
hNor->deviceID[0] = (*(CSL_VUint16*)(hNor->CSnBASE+0x00));/*man id*/
hNor->deviceID[1] = (*(CSL_VUint16*)(hNor->CSnBASE+0x01));/*dev id*/
hNor->deviceID[2] = (*(CSL_VUint16*)(hNor->CSnBASE+0x05));/*rcr*/
}
else if (CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
if(CSL_NOR_8_BIT == hNor->norWidth)
{
hNor->deviceID[0] = (*(CSL_VUint16*)(hNor->CSnBASE+0x00));/*man id*/
hNor->deviceID[1] = (*(CSL_VUint16*)(hNor->CSnBASE+0x02));/*dev id-1*/
hNor->deviceID[2] = (*(CSL_VUint16*)(hNor->CSnBASE+0x1C));/*dev id-2*/
hNor->deviceID[3] = (*(CSL_VUint16*)(hNor->CSnBASE+0x1E));/*dev id-3*/
}
else if(CSL_NOR_16_BIT == hNor->norWidth)
{
hNor->deviceID[0] = (*(CSL_VUint16*)(hNor->CSnBASE+0x00));/*man id*/
hNor->deviceID[1] = (*(CSL_VUint16*)(hNor->CSnBASE+0x01));/*dev id-1*/
hNor->deviceID[2] = (*(CSL_VUint16*)(hNor->CSnBASE+0x0E));/*dev id-2*/
hNor->deviceID[3] = (*(CSL_VUint16*)(hNor->CSnBASE+0x0F));/*dev id-3*/
}
/*Reset to exit auto-select mode for AMD*/
*(CSL_VUint16*)(hNor->CSnBASE+0x0) = 0xF0;
}
return status;
}
/* This is available only for Intel Command Based*/
/*The second arg is long because it is the block address not the block number*/
static CSL_Status NOR_readAndClearStatus(CSL_NorHandle hNor, Uint32 dBlockOffset, Uint16 *norStatus)
{
CSL_Status status;
status = CSL_SOK;
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{/* Read status register */
*(CSL_VUint16*)(hNor->CSnBASE+dBlockOffset) = 0x70;
__asm(" NOP");
__asm(" NOP");
__asm(" NOP");
*norStatus = (*(CSL_VUint16*)(hNor->CSnBASE+dBlockOffset));
/* Clear status register */
*(CSL_VUint16*)(hNor->CSnBASE+dBlockOffset) = 0x50;
__asm(" NOP");
__asm(" NOP");
__asm(" NOP");
}
return status;
}
CSL_Status NOR_readCFI(CSL_NorHandle hNor)
{
CSL_Status status;
status = CSL_SOK;
/* Read CFI */
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
*(CSL_VUint16*)(hNor->CSnBASE+0x10) = 0x98;
}
else if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
if(CSL_NOR_8_BIT == hNor->norWidth)
{
*(CSL_VUint16*)(hNor->CSnBASE+0xAA) = 0x98;
}
else if(CSL_NOR_16_BIT == hNor->norWidth)
{
*(CSL_VUint16*)(hNor->CSnBASE+0x55) = 0x98;
}
}
__asm(" NOP");
__asm(" NOP");
__asm(" NOP");
hNor->cfiData[0] = (*(CSL_VUint16*)(hNor->CSnBASE+0x26));
hNor->cfiData[1] = (*(CSL_VUint16*)(hNor->CSnBASE+0x27));
hNor->cfiData[2] = (*(CSL_VUint16*)(hNor->CSnBASE+0x28));
hNor->cfiData[3] = (*(CSL_VUint16*)(hNor->CSnBASE+0x29));
hNor->cfiData[4] = (*(CSL_VUint16*)(hNor->CSnBASE+0x2a));
hNor->cfiData[5] = (*(CSL_VUint16*)(hNor->CSnBASE+0x2b));
hNor->cfiData[6] = (*(CSL_VUint16*)(hNor->CSnBASE+0x2c));
hNor->cfiData[7] = (*(CSL_VUint16*)(hNor->CSnBASE+0x2d));
hNor->cfiData[8] = (*(CSL_VUint16*)(hNor->CSnBASE+0x2e));
if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
/*Reset to exit Read-CFI mode in AMD*/
*(CSL_VUint16*)(hNor->CSnBASE+0x0) = 0xF0;
}
return status;
}
CSL_Status NOR_readBlockLockStatus(CSL_NorHandle hNor, Uint16 *blockLockStatus)
{
CSL_Status status;
Uint16 blockLockConf;
Uint32 i;
status = CSL_SOK;
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
*(CSL_VUint16*)hNor->CSnBASE = 0x90;
}
else if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
if(CSL_NOR_8_BIT == hNor->norWidth)
{
*(CSL_VUint16*)(hNor->CSnBASE+0xAAA) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0x55;
*(CSL_VUint16*)(hNor->CSnBASE+0xAAA) = 0x90;
}
else if(CSL_NOR_16_BIT == hNor->norWidth)
{
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+0x2AA) = 0x55;
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0x90;
}
}
__asm(" NOP");
__asm(" NOP");
__asm(" NOP");
for(i=0; i<=130/*hNor->numOfBlocks*/; i++)//taking only first 130 blocks
{
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
blockLockConf = (*(CSL_VUint16*)(hNor->CSnBASE+(i*hNor->blockLength)+0x2));
}
else if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
/*This is the same for 8-bit and 16-bit*/
blockLockConf = (*(CSL_VUint16*)(hNor->CSnBASE+((i*hNor->blockLength)&0xFFFFFF00)+0x02));
}
if(blockLockConf & 0x1)
{
/*Block is LOCKED*/
blockLockStatus[i/16] |= (0x1 << (i%16));
/*If bit[1] is set then Block is LOCKED-DOWN*/
}
else
{
/*Block is Unlocked*/
blockLockStatus[i/16] &= (0x1 << (i%16));
}
}
return status;
}
CSL_Status NOR_unlockBlock(CSL_NorHandle hNor, Uint16 blockNum, Uint16 *blockLockStatus)
{
CSL_Status status;
Uint32 dBlockAddress;
status = CSL_SOK;
dBlockAddress = (Uint32)blockNum * hNor->blockLength;
/* Lock Block Setup Command */
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
*(CSL_VUint16*)(hNor->CSnBASE+dBlockAddress) = 0x60;
}
else if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
}
/* Unlock Block Command */
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
*(CSL_VUint16*)(hNor->CSnBASE+dBlockAddress) = 0xD0;
}
else if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
}
/* Read ID Command */
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
*(CSL_VUint16*)hNor->CSnBASE = 0x90;
}
else if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
}
__asm(" NOP");
__asm(" NOP");
__asm(" NOP");
*blockLockStatus = (*(CSL_VUint16*)(hNor->CSnBASE+dBlockAddress+0x2));
return status;
}
CSL_Status NOR_readArray(CSL_NorHandle hNor, Uint16 blockNum, Uint16 wordOffset)
{
CSL_Status status;
Uint32 dWordAddress;
status = CSL_SOK;
dWordAddress = ((Uint32)blockNum * hNor->blockLength) + (Uint32)wordOffset;
/* Read Array Command */
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress) = 0xFF;
}
else if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
/*No unlock or command cycle required when bank is reading array data
Issuing a reset command, as it may be required in some cases and
it doesn't matter in others*/
/* This is the same for 8 and 16 bit devices*/
*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress) = 0xF0;
}
__asm(" NOP");
__asm(" NOP");
__asm(" NOP");
return status;
}
CSL_Status NOR_enterUnlockBypassedMode(CSL_NorHandle hNor)
{
CSL_Status status;
status = CSL_SOK;
/*This is only for amd cmdset based nor device*/
/*Unlock bypass is possible only for wordWrite, blockErase and chipErase*/
if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
if(CSL_NOR_8_BIT == hNor->norWidth)
{
*(CSL_VUint16*)(hNor->CSnBASE+0xAAA) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0x55;
*(CSL_VUint16*)(hNor->CSnBASE+0xAAA) = 0x20;
}
else if(CSL_NOR_16_BIT == hNor->norWidth)
{
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+0x2AA) = 0x55;
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0x20;
}
hNor->enableUnlockSeq = FALSE;
}
return status;
}
CSL_Status NOR_exitUnlockBypassedMode(CSL_NorHandle hNor)
{
CSL_Status status;
status = CSL_SOK;
/*This is only for amd cmdset based nor device*/
/*Unlock bypass is possible only for wordWrite, blockErase and chipErase*/
if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
/*This is the same for 8-bit and 16-bit devices*/
*(CSL_VUint16*)(hNor->CSnBASE+0x0) = 0x90;
*(CSL_VUint16*)(hNor->CSnBASE+0x0) = 0x00;
}
hNor->enableUnlockSeq = TRUE;
return status;
}
CSL_Status NOR_eraseBlock(CSL_NorHandle hNor, Uint16 blockNum,
Uint16 statusMode, Uint16 *eraseStatus)
{
CSL_Status status;
volatile Uint16 pollStatus;
volatile Uint16 dqNValue;
Uint32 dBlockAddress;
status = CSL_SOK;
dBlockAddress = (Uint32)blockNum*hNor->blockLength;
/* Block erase setup */
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
*(CSL_VUint16*)(hNor->CSnBASE+dBlockAddress) = 0x20;
}
else if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
if(CSL_NOR_8_BIT == hNor->norWidth)
{
if(hNor->enableUnlockSeq)
{
*(CSL_VUint16*)(hNor->CSnBASE+0xAAA) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0x55;
}
*(CSL_VUint16*)(hNor->CSnBASE+0xAAA) = 0x80;
}
else if(CSL_NOR_16_BIT == hNor->norWidth)
{
if(hNor->enableUnlockSeq)
{
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+0x2AA) = 0x55;
}
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0x80;
}
}
/* Block erase confirm */
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
*(CSL_VUint16*)(hNor->CSnBASE+dBlockAddress) = 0xD0;
}
else if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
if((CSL_NOR_8_BIT == hNor->norWidth) && hNor->enableUnlockSeq)
{
*(CSL_VUint16*)(hNor->CSnBASE+0xAAA) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0x55;
}
else if((CSL_NOR_16_BIT == hNor->norWidth) && hNor->enableUnlockSeq)
{
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+0x2AA) = 0x55;
}
*(CSL_VUint16*)(hNor->CSnBASE+dBlockAddress) = 0x30;
}
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
do {
status = NOR_readAndClearStatus(hNor, 0, eraseStatus);
} while(!(*eraseStatus & 0x0080));
}
else if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
#if 0
/*Check DQ3 for Erase Timer timedout condition*/
do {
dqNValue = (*(CSL_VUint16*)(hNor->CSnBASE+dBlockAddress));
} while(0x0008 != (dqNValue & 0x0008));
#endif
/*After erase timer times out. erase algorithm begins*/
if(CSL_NOR_DQ7_STATUS == statusMode)
{
do {
pollStatus = (*(CSL_VUint16*)(hNor->CSnBASE+dBlockAddress));
if(0x0080 == (pollStatus&0x0080))
{/*If DQ7=1 then erase complete or erase suspended state*/
break;
}
} while(0x0020 != (pollStatus&0x0020));/*Program/Erase/Write-to-Buffer timedout*/
if(0x0020 == (pollStatus&0x0020))/*A timeout happened*/
{
pollStatus = (*(CSL_VUint16*)(hNor->CSnBASE+dBlockAddress));
if(0x0080 == (pollStatus&0x0080))
{
status = CSL_SOK;
}
else
{
status = CSL_EMMCSD_TIMEOUT;
/*Issue a reset to change to read array mode*/
*(CSL_VUint16*)(hNor->CSnBASE+0x0) = 0xF0;
}
}
}/*DQ7 status*/
else if (CSL_NOR_DQ6_STATUS == statusMode)
{
do {
dqNValue = (*(CSL_VUint16*)(hNor->CSnBASE+dBlockAddress));
pollStatus = (*(CSL_VUint16*)(hNor->CSnBASE+dBlockAddress));
#if 0
if((dqNValue&0x0004) == (pollStatus&0x0004))
{/*DQ2 not toggling. This sector is not for erase*/
/*As we are checking the status soon after the erase command,
this condition shall always be in the toggle state*/
break;
}
#endif
if((dqNValue&0x0040) == (pollStatus&0x0040))
{/*DQ6 not toggling. Erase suspend or Erase complete*/
break;
}
} while(0x0020 != (pollStatus&0x0020));/*Program/Erase/Write-to-Buffer timedout*/
if(0x0020 == (pollStatus&0x0020))/*A timeout happened*/
{
dqNValue = (*(CSL_VUint16*)(hNor->CSnBASE+dBlockAddress));
pollStatus = (*(CSL_VUint16*)(hNor->CSnBASE+dBlockAddress));
if((dqNValue&0x0040) == (pollStatus&0x0040))
{
status = CSL_SOK;
}
else
{
status = CSL_EMMCSD_TIMEOUT;
/*Issue a reset to change to read array mode*/
*(CSL_VUint16*)(hNor->CSnBASE+0x0) = 0xF0;
}
}
}/*DQ6 status*/
*eraseStatus = pollStatus;
}/*amd cmdset*/
return status;
}
/*Uint16 is ok for wordOffset as we deal with 64KWord NOR device. Range is 0x0-0xFFFF*/
CSL_Status NOR_writeWord(CSL_NorHandle hNor, Uint16 blockNum,
Uint16 wordOffset, Uint16 wordData,
Uint16 statusMode, Uint16 *writeStatus)
{
CSL_Status status;
Uint32 dWordAddress;
volatile Uint16 pollStatus;
volatile Uint16 dqNValue;
status = CSL_SOK;
dWordAddress = ((Uint32)blockNum * hNor->blockLength) + (Uint32)wordOffset;
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress) = 0x40;
}
else if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
if(CSL_NOR_8_BIT == hNor->norWidth)
{
if(hNor->enableUnlockSeq)
{
*(CSL_VUint16*)(hNor->CSnBASE+0xAAA) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0x55;
}
*(CSL_VUint16*)(hNor->CSnBASE+0xAAA) = 0xA0;
}
else if(CSL_NOR_16_BIT == hNor->norWidth)
{*(CSL_VUint16*)(hNor->CSnBASE+0x0) = 0xF0;
if(hNor->enableUnlockSeq)
{
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+0x2AA) = 0x55;
}
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0xA0;
}
}
*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress) = wordData;
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
do {
status = NOR_readAndClearStatus(hNor, 0, writeStatus);
} while(!((*writeStatus) & 0x0080));
}
else if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
if(CSL_NOR_DQ7_STATUS == statusMode)
{
dqNValue = wordData&0x0080;
do {
pollStatus = (*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress));
if(dqNValue == (pollStatus&0x0080))
{/*If DQ7 read, is equal to DQ7 written then write is complete*/
break;
}
} while(0x0020 != (pollStatus&0x0020));/*Program/Erase/Write-to-Buffer timedout*/
if(0x0020 == (pollStatus&0x0020))/*A timeout happened*/
{
pollStatus = (*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress));
if(dqNValue == (pollStatus&0x0080))
{
status = CSL_SOK;
}
else
{
status = CSL_EMMCSD_TIMEOUT;
/*Issue a reset to change to read array mode*/
*(CSL_VUint16*)(hNor->CSnBASE+0x0) = 0xF0;
}
}
}/*DQ7 status*/
else if (CSL_NOR_DQ6_STATUS == statusMode)
{
do {
dqNValue = (*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress));
pollStatus = (*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress));
if((dqNValue&0x0040) == (pollStatus&0x0040))
{/*If DQ6 stopped its toggle then write is complete*/
break;
}
} while(0x0020 != (pollStatus&0x0020));/*Program/Erase/Write-to-Buffer timedout*/
if(0x0020 == (pollStatus&0x0020))/*A timeout happened*/
{
/*read twice. will the compiler optimize??*/
dqNValue = (*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress));
pollStatus = (*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress));
if((dqNValue&0x0040) == (pollStatus&0x0040))
{/*If DQ6 stopped its toggle then write is complete*/
status = CSL_SOK;
}
else
{
status = CSL_EMMCSD_TIMEOUT;
/*Issue a reset to change to read array mode*/
*(CSL_VUint16*)(hNor->CSnBASE+0x0) = 0xF0;
}
}
}/*DQ6 status*/
*writeStatus = pollStatus;
}/*amd cmdset*/
return status;
}
CSL_Status NOR_writeBufferSetup(CSL_NorHandle hNor, Uint16 blockNum,
Uint16 wordOffset, Uint16 numOfWords)
{
CSL_Status status;
Uint32 dWordAddress;
Uint32 dBlockAddress;
Uint16 writeStatus;
status = CSL_SOK;
if(hNor->writeBufferSize < numOfWords)
status = CSL_ESYS_FAIL;
dBlockAddress = (Uint32)blockNum * hNor->blockLength;
dWordAddress = ((Uint32)blockNum * hNor->blockLength) + (Uint32)wordOffset;
/* Buffered Program Setup command */
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress) = 0xE8;
do {/* Wait for Buffer Ready on SR[7]*/
#if 0
status = NOR_readAndClearStatus(hNor, dWordAddress, &writeStatus);
#endif
writeStatus = *(CSL_VUint16*)(hNor->CSnBASE+dWordAddress);
} while(!(writeStatus & 0x80));
/* Write the number of Words to be written */
*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress) = numOfWords-1;
}
else if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
if(CSL_NOR_8_BIT == hNor->norWidth)
{
*(CSL_VUint16*)(hNor->CSnBASE+0xAAA) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0x55;
}
else if(CSL_NOR_16_BIT == hNor->norWidth)
{
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+0x2AA) = 0x55;
}
*(CSL_VUint16*)(hNor->CSnBASE+dBlockAddress) = 0x25;
*(CSL_VUint16*)(hNor->CSnBASE+dBlockAddress) = numOfWords-1;
}/*amd cmdset*/
return status;
}
CSL_Status NOR_writeBufferComplete(CSL_NorHandle hNor, Uint16 blockNum,
Uint16 wordOffset, Uint16 numOfWords,
Uint16 *writeBuffer, Uint16 statusMode,
Uint16 *writeStatus)
{
CSL_Status status;
Uint32 dWordAddress;
Uint32 dBlockAddress;
volatile Uint16 pollStatus=0;
volatile Uint16 dqNValue=0;
status = CSL_SOK;
if(hNor->writeBufferSize < numOfWords)
status = CSL_ESYS_FAIL;
dBlockAddress = (Uint32)blockNum * hNor->blockLength;
dWordAddress = ((Uint32)blockNum * hNor->blockLength) + (Uint32)wordOffset;
/* Buffered Program Confirm command */
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
*(CSL_VUint16*)(hNor->CSnBASE+dBlockAddress) = 0xD0;
}
else if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
*(CSL_VUint16*)(hNor->CSnBASE+dBlockAddress) = 0x29;
}
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
do { /*Wait for Buffer Ready on SR[7]*/
status = NOR_readAndClearStatus(hNor, 0, writeStatus);
} while(!((*writeStatus) & 0x80));
}
else if(CSL_NOR_AMD_STD_CMDSET & hNor->commandSet)
{
if(CSL_NOR_DQ7_STATUS == statusMode)
{
// dqNValue = writeBuffer[numOfWords-1] & 0x0080;/*This is not working properly, with s/m test on QT - Pramod*/
dqNValue = *(writeBuffer+numOfWords-1);
dqNValue &= 0x0080;
do {
pollStatus = (*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress+numOfWords-1));
if(dqNValue == (pollStatus&0x0080))
{/*If DQ7 read, is equal to DQ7 written then write is complete*/
break;
}
if(0x0002 == (pollStatus&0x0002))
{/*When DQ1=1, it means that the Write-to-buffer programming has aborted*/
/*Abort write-to-buffer*/
if(CSL_NOR_8_BIT == hNor->norWidth)
{
*(CSL_VUint16*)(hNor->CSnBASE+0xAAA) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress) = 0x55;
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0xF0;
}
else if(CSL_NOR_16_BIT == hNor->norWidth)
{
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+0x2AA) = 0x55;
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0xF0;
}
status = CSL_ESYS_FAIL;
break;
}
} while(0x0020 != (pollStatus&0x0020));/*Program/Erase/Write-to-Buffer timedout*/
if(0x0020 == (pollStatus&0x0020))/*A timeout happened*/
{
pollStatus = (*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress+numOfWords-1));
if(dqNValue == (pollStatus&0x0080))
{
status = CSL_SOK;
}
else
{
status = CSL_EMMCSD_TIMEOUT;
/*Issue a reset to change to read array mode*/
*(CSL_VUint16*)(hNor->CSnBASE+0x0) = 0xF0;
}
}
/*DQ1=1, is handled below*/
}/*DQ7 status*/
else if (CSL_NOR_DQ6_STATUS == statusMode)
{
do {
dqNValue = (*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress+(Uint32)(numOfWords-1)));
pollStatus = (*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress+(Uint32)(numOfWords-1)));
if((dqNValue&0x0040) == (pollStatus&0x0040))
{/*If DQ6 stopped its toggle then write is complete*/
break;
}
if(0x0002 == (pollStatus&0x0002))
{/*When DQ1=1, it means that the Write-to-buffer programming has aborted*/
/*Abort write-to-buffer*/
if(CSL_NOR_8_BIT == hNor->norWidth)
{
*(CSL_VUint16*)(hNor->CSnBASE+0xAAA) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress) = 0x55;
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0xF0;
}
else if(CSL_NOR_16_BIT == hNor->norWidth)
{
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0xAA;
*(CSL_VUint16*)(hNor->CSnBASE+0x2AA) = 0x55;
*(CSL_VUint16*)(hNor->CSnBASE+0x555) = 0xF0;
}
status = CSL_ESYS_FAIL;
break;
}
} while(0x0020 != (pollStatus&0x0020));/*Program/Erase/Write-to-Buffer timedout*/
if(0x0020 == (pollStatus&0x0020))/*A timeout happened*/
{
/*read twice. will the compiler optimize??*/
dqNValue = (*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress+(Uint32)(numOfWords-1)));
pollStatus = (*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress+(Uint32)(numOfWords-1)));
if((dqNValue&0x0040) == (pollStatus&0x0040))
{/*If DQ6 stopped its toggle then write is complete*/
status = CSL_SOK;
}
else
{
status = CSL_EMMCSD_TIMEOUT;
/*Issue a reset to change to read array mode*/
*(CSL_VUint16*)(hNor->CSnBASE+0x0) = 0xF0;
}
}
/*DQ1=1, is handled below*/
}/*DQ6 status*/
*writeStatus = pollStatus;
}/*amd cmdset*/
return status;
}
/* ============================================================================
* Copyright (c) 2008-2016 Texas Instruments Incorporated.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/** @file CSL_EMIF_NOR_CpuTransfer.c
*
* @brief EMIF functional layer polled mode example source file
*
* \page page13 CSL EMIF EXAMPLE DOCUMENTATION
*
* \section EMIF5 EMIF EXAMPLE5 - NOR CPU MODE TEST
*
* \subsection EMIF5x TEST DESCRIPTION:
* NOTE: NOR Flash on-board C5517 EVM is a 128Mbit Spansion flash S29Gl128S11DHIV20.
*
* In CSL_NOR_Test.h, comment #define EVM5515 1 and Uncomment #define EVM5517 1 if running on C5517 EVM.
* In CSL_NOR_Test.h, comment #define EVM5517 1 and Uncomment #define EVM5515 1 if running on C5515 EVM.
*
* 1. Configure EMIF, start the clock and bring it out of reset.
* 2. Configure the NOR flash parameters in EMIF registers such as AWCCR1, AWCCR2, ACS2CR1, ACS2CR2, etc.
* 3. Read the manufacturer and device IDs.
* 4. Check if the test-block is blocked for r/w or not.
* 5. Erase the block and prepare it for r/w.
* 6. Write a block of data to the selected block in the NOR Flash.
* 7. Read a block of data from the test block.
* 8. Perform a comparison of read and written data. There should be no mismatch.
*
* NOTE: This test assumes that
* a. NOR flash is connected to emif cs2 on C5515 EVM and on C5517 EVM.
* This example may not work with connections that are different from above
* connections.
*
* NOTE: THIS TEST HAS BEEN DEVELOPED TO WORK WITH CHIP VERSIONS C5515 AND
* C5517. MAKE SURE THAT PROPER CHIP VERSION MACRO IS DEFINED IN THE FILE
* c55xx_csl\inc\csl_general.h.
*
* \subsection EMIF5y TEST PROCEDURE:
* @li Open the CCS and connect the target (C5515/C5517 EVM)
* @li Open the project "CSL_NOR_PollExample_Out.pjt" and build it
* @li Load the program on to the target
* @li Set the PLL frequency to 12.288MHz
* @li Run the program and observe the test result
* @li Repeat the test at the following PLL frequencies
* C5515: 60MHz and 100MHz
* C5517: 60MHz, 100MHz, 150MHz and 200MHz
* @li Repeat the test in Release mode
*
* \subsection EMIF5z TEST RESULT:
* @li All the CSL APIs should return success
* @li Read and write data buffer comparison should be successful.
*
* ============================================================================
*/
/* ============================================================================
* Revision History
* ================
* 05-Sep-2008 Created
* 10-Mar-2016 Updates to header
* ============================================================================
*/
#include <stdio.h>
#include <string.h>
#include <csl_types.h>
#include "inc\csl_nor.h"
#include <csl_dma.h>
#include "CSL_NOR_Test.h"
/* Save the lock status of 130 blocks */
Uint16 gBlockLockStatus[CSL_NOR_BLOCKLOCK_STATUS_ARRAY];
/* Align is for optimum performance while using Buffered and BEFP Programming */
#ifdef CSL_NOR_USE_ALIGNED_BUFFER
#pragma DATA_ALIGN(gNorReadBuffer,CSL_NOR_BUFFER_ALIGN_BOUNDARY); /*32-byte boundary and it works*/
#endif
Uint16 gNorReadBuffer[CSL_NOR_TEST_BUFFER_WORD_COUNT];
#ifdef CSL_NOR_USE_ALIGNED_BUFFER
#pragma DATA_ALIGN(gNorWriteBuffer,CSL_NOR_BUFFER_ALIGN_BOUNDARY); /*32-byte boundary and it works*/
#endif
Uint16 gNorWriteBuffer[CSL_NOR_TEST_BUFFER_WORD_COUNT];
CSL_Status CSL_norCpuTransferTest(void)
{
CSL_Status status;
CSL_NorObj norObj;
CSL_NorHandle hNor;
Uint16 norStatus;
Uint16 blockNum;
Uint32 i;
Uint32 dWordAddress;
Uint16 wordOffset;
#ifdef EVM5515
CSL_NorAsyncCfg norAsyncCfg = PC28F128P30T85_ASYNCCFG_DEFAULT;
CSL_NorAsyncWaitCfg norAsyncWaitCfg = PC28F128P30T85_ASYNCWAITCFG_DEFAULT;
CSL_NorConfig norCfg = PC28F128P30T85_NORCFG_POLLED;
#elif EVM5517
CSL_NorAsyncCfg norAsyncCfg = S29GL128S11DHIV20_ASYNCCFG_DEFAULT;
CSL_NorAsyncWaitCfg norAsyncWaitCfg = S29GL128S11DHIV20_ASYNCWAITCFG_DEFAULT;
CSL_NorConfig norCfg = S29GL128S11DHIV20_NORCFG_POLLED;
#endif
status = CSL_SOK;
hNor = &norObj;
norCfg.asyncWaitCfg = &norAsyncWaitCfg;
norCfg.asyncCfg = &norAsyncCfg;
memset(&gNorReadBuffer, 0x0, sizeof(gNorReadBuffer));
memset(&gNorWriteBuffer, 0x0, sizeof(gNorWriteBuffer));
for(i=0; i<CSL_NOR_TEST_BUFFER_WORD_COUNT; i++)
{
gNorWriteBuffer[i] = i;
}
status = NOR_setup(&norObj, 0);
if(CSL_SOK != status)
{
printf("SETUP: Bad Status\n");
}
status = NOR_emifResetAndClock(hNor);
if(CSL_SOK != status)
{
printf("NOR EMIF RST & CLK: Bad Status\n");
}
/*norCfg was filled when it was defined*/
status = NOR_setupEmifChipSelect(hNor, &norCfg);
if(CSL_SOK != status)
{
printf("SETUP EMIF CS: Bad Status\n");
}
memset(hNor->deviceID, 0x0, sizeof(hNor->deviceID));
status = NOR_readId(hNor);
if(CSL_SOK != status)
{
printf("READ ID: Bad Status\n");
}
if((0xFF == hNor->deviceID[1]) || (0xFFFF == hNor->deviceID[1]))
{
printf("No Device Found\n");
}
else
{
printf("Manufacturer ID %x\n", hNor->deviceID[0]);
printf("Device ID %x\n", hNor->deviceID[1]);
}
memset(hNor->cfiData, 0x0, sizeof(hNor->cfiData));
status = NOR_readCFI(hNor);
if(CSL_SOK != status)
{
printf("READ CFI: Bad Status\n");
}
/*Read Block Lock Status */
memset(&gBlockLockStatus, 0x0, sizeof(gBlockLockStatus));
status = NOR_readBlockLockStatus(hNor, &gBlockLockStatus[0]);
if(CSL_SOK != status)
{
printf("READ BLOCK LOCK STATUS: Bad Status\n");
}
/*Unlock the Block*/
blockNum = CSL_NOR_TEST_BLOCK_NUM;
if(gBlockLockStatus[CSL_NOR_TEST_BLOCK_NUM/16] & (0x1 << (CSL_NOR_TEST_BLOCK_NUM%16)))
{
status = NOR_unlockBlock(hNor, blockNum, &norStatus);
if(CSL_SOK != status)
{
printf("UNLOCK BLOCK: Bad Status\n");
}
if(norStatus & 0x1)
{
printf("Block-%d is LOCKED\n", blockNum);
if(norStatus & 0x2)
printf("Block-%d is LOCKED-DOWN\n", blockNum);
else
printf("Block-%d is not Locked-Down\n", blockNum);
}
else
{
printf("Block-%d is Unlocked\n", blockNum);
}
}
else
{
printf("Block-%d was Unlocked\n", blockNum);
}
/* Erase the Block */
blockNum = CSL_NOR_TEST_BLOCK_NUM;
norStatus = 0;
//status = NOR_eraseBlock(hNor, blockNum, CSL_NOR_DQ7_STATUS, &norStatus);
status = NOR_eraseBlock(hNor, blockNum, CSL_NOR_DQ6_STATUS, &norStatus);
if(CSL_SOK == status)
{
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
if(norStatus & 0x20)
{
printf("ERASE: Failed\n");
if(norStatus & 0x8)
printf("ERASE: Vpp range Error\n");
if((norStatus & 0x30) == 0x30)
printf("ERASE: Command sequence Error\n");
if(norStatus & 0x2)
printf("ERASE: Block Locked Error\n");
}
}
else
{
printf("ERASE: Success\n");
}
}
else
{
printf("NOR_eraseBlock: Failed\n");
}
/*Write the Block Using CPU*/
blockNum = CSL_NOR_TEST_BLOCK_NUM;
for(i=0; i<CSL_NOR_TEST_BUFFER_WORD_COUNT; i++)
{
//status = NOR_writeWord(hNor, blockNum, (Uint16)i, gNorWriteBuffer[i], CSL_NOR_DQ7_STATUS, &norStatus);
status = NOR_writeWord(hNor, blockNum, (Uint16)i, gNorWriteBuffer[i], CSL_NOR_DQ6_STATUS, &norStatus);
if(CSL_SOK == status)
{
if(CSL_NOR_INTEL_STD_CMDSET & hNor->commandSet)
{
if(norStatus & 0x10)
{
printf("PROGRAM: Failed\n");
if(norStatus & 0x8)
printf("PROGRAM: Vpp range Error\n");
if((norStatus & 0x30) == 0x30)
printf("PROGRAM: Command sequence Error\n");
if(norStatus & 0x2)
printf("PROGRAM: Block Locked Error\n");
break;
}
}
}
else
{
printf("WRITE WORD: Bad Status\n");
break;
}
}
if(CSL_NOR_TEST_BUFFER_WORD_COUNT == i)
{
printf("PROGRAM: Success\n");
}
/*Read the Block Using CPU*/
blockNum = CSL_NOR_TEST_BLOCK_NUM;
wordOffset = CSL_NOR_TEST_WORD_OFFSET;
status = NOR_readArray(hNor, blockNum, wordOffset);
if(CSL_SOK != status)
{
printf("READ ARRAY: Bad Status\n");
}
blockNum = CSL_NOR_TEST_BLOCK_NUM;
wordOffset = CSL_NOR_TEST_WORD_OFFSET;
dWordAddress = ((Uint32)blockNum * hNor->blockLength) + (Uint32)wordOffset;
for(i=0;i<CSL_NOR_TEST_BUFFER_WORD_COUNT;i++)
{
gNorReadBuffer[i] = (*(CSL_VUint16*)(hNor->CSnBASE+dWordAddress+i));
}
/*Compare and print result*/
for(i=0;i<CSL_NOR_TEST_BUFFER_WORD_COUNT;i++)
{
if(gNorReadBuffer[i] != gNorWriteBuffer[i])
{
printf("COMPARE: FAILED Data doesn't match at %d\n", i);
break;
}
}
if(CSL_NOR_TEST_BUFFER_WORD_COUNT == i)
{
printf("COMPARE: Success\n");
}
return status;
}
/////INSTRUMENTATION FOR BATCH TESTING -- Part 1 --
///// Define PaSs_StAtE variable for catching errors as program executes.
///// Define PaSs flag for holding final pass/fail result at program completion.
volatile Int16 PaSs_StAtE = 0x0001; // Init to 1. Reset to 0 at any monitored execution error.
volatile Int16 PaSs = 0x0000; // Init to 0. Updated later with PaSs_StAtE when and if
///// program flow reaches expected exit point(s).
/////
/**
* \brief Tests NOR
* \param None
* \param None
*/
void main(void)
{
#if (defined(CHIP_C5535) || defined(CHIP_C5545))
printf("\nEnsure CHIP_C5517, CHIP_C5505_C5515 or CHIP_C5504_C5514 is #defined. C5535/C5545 don't have EMIF\n");
#else
CSL_Status status;
status = CSL_SOK;
status = CSL_norCpuTransferTest();
if(0 != status){
printf("NOR_CpuTransfer - Test FAILED!!\n\n");
PaSs_StAtE = 0x0000; // Was intialized to 1 at declaration.
}else
printf("NOR_CpuTransfer - Test Passed\n\n");
/////INSTRUMENTATION FOR BATCH TESTING -- Part 3 --
///// At program exit, copy "PaSs_StAtE" into "PaSs".
PaSs = PaSs_StAtE; //If flow gets here, override PaSs' initial 0 with
///// // pass/fail value determined during program execution.
///// Note: Program should next exit to C$$EXIT and halt, where DSS, under
///// control of a host PC script, will read and record the PaSs' value.
/////
#endif
}
函数CSL_norCpuTransferTest()中用到了几个关键的宏
PC28F128P30T85_ASYNCCFG_DEFAULT
PC28F128P30T85_ASYNCWAITCFG_DEFAULT
PC28F128P30T85_NORCFG_POLLED
它们在CSL_NOR_Test.h中定义。
我现在换成MT28GU256AAA2EGC后，该怎么修改呢？
