各位大神:
目前在测试DSP C6416 跟FPGA之间直连GPIO管教GP8\GP9\GP10\GP11\GP12时,发现DSP将GP8/GP9/GP10/GP11/GP12配置为输出,
且周期1s设置GP8/GP9/GP10/GP11/GP12管脚高低输出跳变,FPGA端检测不到GP8/GP9/GP10/GP11/GP12信号变化,具体测试设置方法如下红色字体描述,请各位高手指点,谢谢!!
6416 GPIO管脚配置如下:
#define GPEN *(volatile Uint32*)0x01b00000
#define GPDIR *(volatile Uint32*)0x01b00004
#define GPVAL *(volatile Uint32*)0x01b00008
GPEN |= ((1 <<8) | (1 <<9) | (1 << 10)|(1<<11)|(1<<12));
GPDIR |= ((1 <<8) | (1 <<9) | (1 << 10)|(1<<11)|(1<<12));
延迟1S
/*拉低管脚*/
GPVAL &= 0xE0FF;
延迟1S
GPVAL |= 0x1F00;