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调试的是自己做的板子仅修改了GEL关于ddr大小及PHY、EMIF部分,ccs的ddrtest可通过,且能简单操作gpio输入输出的拉高拉低,但涉及MMU函数及CACHE函数时就会崩掉,调试的程序参考的starterware的程序,在开发板上是能使用的,但在我自己的板子就不行。
gel修改内容如下:
//******* //DDR3 PHY parameters //**********
#define CMD_PHY_CTRL_SLAVE_RATIO 0x00000100
#define CMD_PHY_INVERT_CLKOUT 0x00000001
#define DATA_PHY_RD_DQS_SLAVE_RATIO 0x00000040
#define DATA_PHY_FIFO_WE_SLAVE_RATIO 0x00000103
#define DATA_PHY_WR_DQS_SLAVE_RATIO 0x00000081
#define DATA_PHY_WR_DATA_SLAVE_RATIO 0x000000C1
#define DDR_IOCTRL_VALUE 0x0000018B //
************** //EMIF parameters //********************
#define ALLOPP_DDR3_READ_LATENCY 8
#define ALLOPP_DDR3_SDRAM_TIMING1 0x0AAAD4DB
#define ALLOPP_DDR3_SDRAM_TIMING2 0x24437FDA
#define ALLOPP_DDR3_SDRAM_TIMING3 0x50FFE3FF
#define ALLOPP_DDR3_SDRAM_CONFIG 0x61A052B2
#define ALLOPP_DDR3_REF_CTRL 0x00000C30
#define ALLOPP_DDR3_ZQ_CONFIG 0x50074BE1
在初始化这一不就已经跑飞。
/* Setup the MMU and do necessary MMU configurations. */
MMUConfigAndEnable();
/* Enable all levels of CACHE. */
CacheEnable(CACHE_ALL);
void MMUInit(unsigned int *masterPt)
{unsigned int idx;
/* Invalidate the TLB entries */
CP15TlbInvalidate();
/* Set domain access rights */
CP15DomainAccessClientSet();
/* Disable TEX remapping, Access Flag usage and alignment check */
CP15ControlFeatureDisable( CP15_CONTROL_TEXREMAP | CP15_CONTROL_ACCESSFLAG | CP15_CONTROL_ALIGN_CHCK | CP15_CONTROL_MMU); /* Configure the TTB Control register to use only TTB0 */
CP15TtbCtlTtb0Config();
/* Se the master page table with fault entries */
for(idx = MMU_PAGETABLE_NUM_ENTRY; idx !=0; idx--)
{*masterPt++ = MMU_PAGETABLE_ENTRY_FAULT;}
单步调试在蓝字段不断循环后,ccs软件直接未响应了。
在正常模式下则显示Break at address "0x217ee" with no debug information available, or outside of program code.
请问在哪里更改stack,我并没有找到stack相关的数据,请问是否修改.cmd文件,下面是。cmd文件的代码
-stack 0x0008
/* SOFTWARE STACK SIZE */
-heap 0x2000 /* HEAP AREA SIZE */
-e Entry
--diag_suppress=10063
/* SPECIFY THE SYSTEM MEMORY MAP */
MEMORY {
DDR_MEM :
org = 0x80000000
len = 0x7FFFFFF
/* RAM */
}
/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
SECTIONS
{
.text:Entry : load > 0x80000000
.text : load > DDR_MEM /* CODE */
.data : load > DDR_MEM /* INITIALIZED GLOBAL AND STATIC VARIABLES */
.bss : load > DDR_MEM /* UNINITIALIZED OR ZERO INITIALIZED */
/* GLOBAL & STATIC VARIABLES */
RUN_START(bss_start)
RUN_END(bss_end)
.const : load > DDR_MEM /* GLOBAL CONSTANTS */
.stack : load > 0x87FFFFF0 /* SOFTWARE SYSTEM STACK */
你好,.cmd文件中的.stack无法修改,只能调小为0x0004,但程序依然会跑飞。
当.stack调大于0x0008时,编译程序将会报错:
gmake: Target 'all' not remade because of errors.
warning: The ".stack" section size is required to be aligned to 8 bytes, but the specified size, 0x16, is not.
The aligned size is 0x18"../dmtimerCounter.cmd",
line 87: error: program will not fit into available memory, or the section contains a call site that requires a trampoline that can't be generated for this section.
run placement with alignment fails for section ".stack" size 0x18
你好,
经过修改.stack后MMU函数能正常运行了,不过CacheEnable(CACHE_ALL)函数在正常模式下会跑飞。
若是先在CacheEnable(CACHE_ALL)函数前打断,单步运行完CacheEnable(CACHE_ALL),在正常运行,则程序能实现功能。
正常模式下跑飞时迅速暂停则显示在floop3中循环跑飞。
CP15DCacheFlush:
PUSH {r4-r11}
DMB MRC p15, #1, r0, c0, c0, #1 ;
Read CLID register ANDS r3, r0, #0x7000000 ;
Get Level of Coherency MOV r3, r3, lsr #23
BEQ ffinished
MOV r10, #0
floop1:
ADD r2, r10, r10, lsr #1
MOV r1, r0, lsr r2
AND r1, r1, #7
CMP r1, #2
BLT fskip
MCR p15, #2, r10, c0, c0, #0
ISB
MRC p15, #1, r1, c0, c0, #0
AND r2, r1, #7 ADD r2, r2, #4
LDR r4, _FLD_MAX_WAY
ANDS r4, r4, r1, lsr #3
CLZ r5, r4
LDR r7, _FLD_MAX_IDX
ANDS r7, r7, r1, lsr #13
floop2:
MOV r9, r4
floop3:
ORR r11, r10, r9, lsl r5
ORR r11, r11, r7, lsl r2
MCR p15, #0, r11, c7, c6, #2
SUBS r9, r9, #1
BGE floop3
SUBS r7, r7, #1
BGE floop2
fskip:
ADD r10, r10, #2
CMP r3, r10
BGT floop1
ffinished: DSB
ISB
POP {r4-r11}
BX lr