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[FAQ] SK-TDA4VM: sprr438 中采用 Altium 格式的 PCB 原理图和布局

Part Number: SK-TDA4VM


Q: 我们想使用 SK-TDA4VM PCB 原理图和布局来开始自己的 PCB 设计。尤其是,高速 DDR4 设计和 PMIC 设计会为我们节省大量的设计时间并避免很多风险。遗憾的是,我们有 Altium,但 sprr438.zip 中提供的设计文件都是使用 Cadence 制作的。如果没有安装 Cadence 软件,Altium 将无法导入这些文件。

是否有人可以将设计文件转换为 Altium 格式并提供转换后的文件?并检查生成文件的合理性。


(我担心的是,如果我尝试使用半官方工具转换这些文件,结果会不准确。例如阻抗可能不准确。)

  • A: 我曾尝试将 Allegro 文件导入到 Altium 中,但收到 extracta 超时错误。  如果您可以提供 Altium 所需的特定命令行参数,我可以对 Allegro 文件运行 extracta。

  • Q: 

    我曾尝试使用该方法在 Altium 中寻找,并找到了我添加的两个附件文件:
      Allegro2Altium.bat(我已将其重命名为 .txt,否则我无法上传它的附件。)
      AllegroExportViews.txt。

    下面描述了 Altium 中的导入过程:
    https://www.altium.com/documentation/altium-designer/allegro-import-ad


    但我的 PC 上没有安装 Cadence。

    这有什么用吗?

    # Start of Allegro to Altium Designer Board View
    BOARD
        BOARD_NAME
        BOARD_UNITS
        BOARD_EXTENTS_X1
        BOARD_EXTENTS_Y1
        BOARD_EXTENTS_X2
        BOARD_EXTENTS_Y2
        BOARD_THICKNESS
    END
    # End of Allegro to Altium Designer Board View
    
    # Start of Allegro to Altium Designer Layer View
    LAYER
        LAYER_SORT
        LAYER_SUBCLASS
        LAYER_ARTWORK
        LAYER_USE
        LAYER_CONDUCTOR
        LAYER_DIELECTRIC_CONSTANT
        LAYER_ELECTRICAL_CONDUCTIVITY
        LAYER_MATERIAL
        LAYER_THERMAL_CONDUCTIVITY
        LAYER_THICKNESS
    END
    # End of Allegro to Altium Designer Layer View
    
    #
    # Connectivity - Simple Net list.
    #
    CONNECTIVITY
      NET_NAME != ''
      CLASS = 'PIN'
      NET_NAME_SORT
      NODE_SORT
      NET_NAME
      REFDES
      PIN_NUMBER
      PIN_NAME
      SUBCLASS
    END
    
    #
    # Net Rules View
    #
    NET
      NET_NAME_SORT
      NET_NAME
      NET_STATUS
      NET_CAPACITANCE
      NET_ETCH_LENGTH
      NET_ETCH_WIDTH_AVERAGE
      NET_IMPEDANCE_AVERAGE
      NET_IMPEDANCE_MAXIMUM
      NET_IMPEDANCE_MINIMUM
      NET_INDUCTANCE
      NET_MANHATTAN_LENGTH
      NET_MANHATTEN_LENGTH
      NET_PATH_LENGTH
      NET_PROPAGATION_DELAY
      NET_RESISTANCE
      NET_VIA_COUNT
      NET_BUS_NAME
      NET_PHYSICAL_TYPE
      NET_PROPAGATION_DELAY
      NET_DIFFERENTIAL_PAIR
      NET_DRIVER_TERM_VAL
      NET_ECL
      NET_ECL_TEMP
      NET_FIXED
      NET_LOAD_TERM_VAL
      NET_RELATIVE_PROPAGATION_DELAY
      
      NET_MAX_BVIA_STAGGER
      NET_MAX_FINAL_SETTLE
      NET_MAX_OVERSHOOT
      NET_MAX_PARALLEL
      
      NET_MAX_VIA_COUNT
      NET_MIN_BVIA_GAP
      NET_MIN_BVIA_STAGGER
      NET_MIN_LINE_WIDTH
      NET_MIN_NOISE_MARGIN
      NET_NET_PHYSICAL_TYPE
      NET_NET_SPACING_TYPE
      NET_NO_GLOSS
      NET_NO_PIN_ESCAPE
      NET_NO_RAT
      NET_NO_RIPUP
      NET_NO_ROUTE
      NET_NO_TEST
      NET_PROBE_NUMBER
      NET_RATSNEST_SCHEDULE
      NET_ROUTE_PRIORITY
      NET_ROUTE_TO_SHAPE
      NET_SAME_NET
      NET_SPACING_TYPE
      NET_STUB_LENGTH
      NET_TS_ALLOWED
      NET_VIA_LIST
      NET_VOLTAGE
      NET_WEIGHT
    
    END
    
    #
    # Pad Stack View
    #
    PAD_DEF
    END
    
    #
    # Board geometries minus symbols.
    #
    FULL_GEOMETRY
    
      CLASS != 'PACKAGE GEOMETRY'
      CLASS
      SUBCLASS
      SYM_TYPE != 'PACKAGE'
      RECORD_TAG
      GRAPHIC_DATA_NAME
      GRAPHIC_DATA_NUMBER
      GRAPHIC_DATA_1
      GRAPHIC_DATA_2
      GRAPHIC_DATA_3
      GRAPHIC_DATA_4
      GRAPHIC_DATA_5
      GRAPHIC_DATA_6
      GRAPHIC_DATA_7
      GRAPHIC_DATA_8
      GRAPHIC_DATA_9
      GRAPHIC_DATA_10
      PIN_NUMBER
      PAD_STACK_NAME
      PAD_SHAPE_NAME
      PAD_TYPE
      PAD_FLASH
      DRILL_HOLE_X
      DRILL_HOLE_Y
      NET_NAME
      PIN_X
      PIN_Y
      VIA_X
      VIA_Y
    
    END
    
    #
    # Extract footprint (symbol) geometries 
    #
    FULL_GEOMETRY
    
    
      SYM_NAME
      SYM_NAME != ''
      SYM_TYPE
      COMP_DEVICE_TYPE
    
      REFDES
    
      CLASS
      SUBCLASS
      RECORD_TAG
      GRAPHIC_DATA_NAME
      GRAPHIC_DATA_NUMBER
      GRAPHIC_DATA_1
      GRAPHIC_DATA_2
      GRAPHIC_DATA_3
      GRAPHIC_DATA_4
      GRAPHIC_DATA_5
      GRAPHIC_DATA_6
      GRAPHIC_DATA_7
      GRAPHIC_DATA_8
      GRAPHIC_DATA_9
      GRAPHIC_DATA_10
      PIN_NUMBER
      PIN_NAME
      PIN_TYPE
      PAD_STACK_NAME
      PAD_SHAPE_NAME
      PAD_TYPE
      PAD_FLASH
      DRILL_HOLE_X
      DRILL_HOLE_Y
      NET_NAME
      PIN_X
      PIN_Y
    
    END
    
    #
    # Symbol Instances.
    #
    SYMBOL
         SYM_TYPE
         SYM_NAME
         REFDES
         SYM_MIRROR
         SYM_ROTATE
         SYM_X
         SYM_Y
         SYM_CENTER_X
         SYM_CENTER_Y
         SYM_LIBRARY_PATH
    END

    extracta.exe %1 AllegroExportViews.txt AllegroBoard.txt AllegroLayer.txt AllegroConnectivity.txt AllegroNetRules.txt AllegroPadStack.txt AllegroGeometry.txt AllegroSymbolDefinitions.txt AllegroSymbolInstances.txt AllegroAddlGeometry.txt AllegroMultiStackup.txt
    COPY AllegroBoard.txt+AllegroLayer.txt+AllegroConnectivity.txt+AllegroNetRules.txt+AllegroPadStack.txt+AllegroGeometry.txt+AllegroSymbolDefinitions.txt+AllegroSymbolInstances.txt+AllegroAddlGeometry.txt+AllegroMultiStackup.txt AllegroASCII.txt
    DEL AllegroBoard.txt AllegroLayer.txt AllegroConnectivity.txt AllegroNetRules.txt AllegroPadStack.txt AllegroGeometry.txt AllegroSymbolDefinitions.txt AllegroSymbolInstances.txt AllegroAddlGeometry.txt AllegroMultiStackup.txt
    MOVE /-Y AllegroASCII.txt %1.alg 

  • Q: 

    我在 Altium 中找到了更多的 AllegroXxxView.txt 文件:

    Allegro2Altium.zip

  • A: 请尝试使用随附的文件。

    PROC112E2_BRD.brd.zip