你好,请问一下TMS320C6748 RMII接口硬件设计需要注意哪些事项呢?
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请看下面的硬件设计文档。
The RMII reference clock (RMII_MHZ_50_CLK) must have a jitter tolerance of 50 ppm or less.
https://www.ti.com/lit/an/sprack9/sprack9.pdf