This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5718: MCASP 回环测试失败

Part Number: AM5718

TI的工程师您好,我在使用AM5718的DSP核测试MCASP回环程序时遇到了一个问题,时钟线能输出我设置的频率对应的波形,同步线也一样,但是AXR引脚无法输出波形,接收缓冲区也无法接收到数据,设置的回调函数也无法触发,我在传输后查看TXSTAT和RXSTAT寄存器的值分别是0x171和0x175,也就是传输出现了错误,我在论坛上看了很多帖子,同时也查看了很多手册,没有找到哪里出了问题,希望您能帮我解答疑惑。

部分测试程序如下:

/*
 * bsp_mcasp.c
 *
 *  Created on: 2022年3月10日
 *      Author: lhy0611
 */

/* XDCtools Header files */
#include <xdc/std.h>
#include <xdc/cfg/global.h>
#include <xdc/runtime/System.h>
#include <xdc/runtime/Error.h>
#include <xdc/runtime/Diags.h>
#include <xdc/runtime/Log.h>
#include <xdc/runtime/Assert.h>
#include <xdc/runtime/Registry.h>
#include <xdc/runtime/IHeap.h>
#include <xdc/runtime/Memory.h>

/* BIOS Header files */
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Clock.h>
#include <ti/sysbios/heaps/HeapMem.h>
#include <ti/sysbios/hal/Hwi.h>
#include <ti/sysbios/knl/Swi.h>
#include <ti/ipc/Ipc.h>
#include <ti/ipc/MessageQ.h>
#include <ti/ipc/MultiProc.h>
#include <ti/sysbios/knl/Semaphore.h>

#include <stdio.h>
#include <ti/csl/example/utils/common/inc/app_utils.h>
#include <ti/csl/soc.h>
#include <ti/csl/hw_types.h>
#include <ti/csl/csl_edma.h>
#include <ti/csl/csl_chip.h>
#include <ti/csl/arch/csl_arch.h>

/* TI-RTOS Header files */
#include <ti/drv/gpio/GPIO.h>
#include <ti/drv/gpio/soc/GPIO_soc.h>

#include <ti/drv/gpio/test/led_blink/src/GPIO_log.h>
#include <ti/drv/gpio/test/led_blink/src/GPIO_board.h>

#include <ti/board/board.h>

#include <ti/osal/osal.h>
#include <ti/osal/CacheP.h>

/* EDMA3 头文件 */
#include <ti/sdo/edma3/drv/edma3_drv.h>
#include <ti/sdo/edma3/rm/edma3_rm.h>
#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>

#include <ti/drv/mcasp/mcasp_drv.h>
#include <ti/drv/mcasp/mcasp_osal.h>
#include <ti/drv/mcasp/soc/mcasp_soc.h>
#include <ti/csl/csl_mcasp.h>
#include <bsp_mcasp.h>
#include <mcasp_cfg.h>
#include <mcasp_drv.h>
#include <mcasp_tune.h>

void Configure_XBAR(void)
{
    /* Mapping the DMA crossbar for McASP DMA_DREQ_(128-120) in to EDMA3_DREQ_0-15.
     * The EDMA3_DREQ_0-15 correspond to (CSL_EDMA3_CHA_MCASP'n'_RX) which are
     * used inside mcasp_soc.c to register EDMA. Please note that the API below takes
     * the mapped DMAReq  with 1 as the base, whereas CSL_EDMA3_CHA_MCASP'n'
     * are with base 0 */
    CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 128,
                         1 + CSL_EDMA3_CHA_MCASP0_RX);
    CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 129,
                         1 + CSL_EDMA3_CHA_MCASP0_TX);
    CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 130,
                         1 + CSL_EDMA3_CHA_MCASP1_RX);
    CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 131,
                         1 + CSL_EDMA3_CHA_MCASP1_TX);
    CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 132,
                         1 + CSL_EDMA3_CHA_MCASP2_RX);
    CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 133,
                         1 + CSL_EDMA3_CHA_MCASP2_TX);
    CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 134,
                         1 + CSL_EDMA3_CHA_MCASP3_RX);
    CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 135,
                         1 + CSL_EDMA3_CHA_MCASP3_TX);
    CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 136,
                         1 + CSL_EDMA3_CHA_MCASP4_RX);
    CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 137,
                         1 + CSL_EDMA3_CHA_MCASP4_TX);
    CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 138,
                         1 + CSL_EDMA3_CHA_MCASP5_RX);
    CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 139,
                         1 + CSL_EDMA3_CHA_MCASP5_TX);
    CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 140,
                         1 + CSL_EDMA3_CHA_MCASP6_RX);
    CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 141,
                         1 + CSL_EDMA3_CHA_MCASP6_TX);
    CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 142,
                         1 + CSL_EDMA3_CHA_MCASP7_RX);
    CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 143,
                         1 + CSL_EDMA3_CHA_MCASP7_RX);
}

void configMcASP_SocHwInfo(void)
{
    /* Configure the interrupts for the McASP Instance MCASP_NUM */
    /* ON Keystone, it involves CIC programming as well.
     * The McASP does that internally, if configured with the correct parameters.
     * Such as muxNum, muxInEvent, muxOutEvent,
     * cpuInEventNum, cpuIntNum
     */
    Mcasp_HwInfo hwInfo;

    Mcasp_socGetInitCfg(MCASP_NUM, &hwInfo);

    if ((hwInfo.rxMuxOutEvent == MCASP_UNASSIGNED_MUX_EVENTNUM)
            || (hwInfo.txMuxOutEvent == MCASP_UNASSIGNED_MUX_EVENTNUM))
    {
#ifdef _TMS320C6X
        /* Choosing a free Crossbar Instance number from Table 17-3. DSP1_INTC Default Interrupt Mapping
         * in the AM572x TRM . Please note that this is fore Core 0 , i.e DSP1 only*/
        /* Freely available cross bar instance numbers for DSP1 */
        hwInfo.txMuxOutEvent = CSL_XBAR_INST_DSP1_IRQ_74;
        hwInfo.rxMuxOutEvent = CSL_XBAR_INST_DSP1_IRQ_75;
        /* The CPU event numbers corresponding to the above  */
        hwInfo.cpuTxEventNumber = 74;
        hwInfo.cpuRxEventNumber = 75;

#endif
    }
    /* Write back */
    Mcasp_socSetInitCfg(MCASP_NUM, &hwInfo);
}
extern EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[];
static void enableEDMAHwEvent(uint32_t edmaNum, uint32_t eventNo)
{
    sampleEdma3GblCfgParams[edmaNum].dmaChannelHwEvtMap[eventNo / 32] |= (1
            << (eventNo % 32));
}

EDMA3_DRV_Handle McaspApp_edmaInit(Mcasp_HwInfo *cfg)
{
    EDMA3_DRV_Handle hEdma;
    EDMA3_DRV_Result edmaResult = 0;

    enableEDMAHwEvent(EDMACC_NUM, CSL_EDMA3_CHA_MCASP2_RX);
    enableEDMAHwEvent(EDMACC_NUM, CSL_EDMA3_CHA_MCASP2_TX);

    hEdma = edma3init(EDMACC_NUM, &edmaResult);

    if (edmaResult != EDMA3_DRV_SOK)
    {
        /* Report EDMA Error
         */
        System_printf("\nEDMA driver initialization unsuccessful\n");
    }
    else
    {
        System_printf("\nEDMA driver initialization successful.\n");
    }

    return hEdma;
}

void mcaspAppCallback(void *arg, MCASP_Packet *ioBuf)
{

    System_printf("\nmcaspAppCallback.\n");
    if (ioBuf->cmd == MCASP_READ)
    {

    }
    else if (ioBuf->cmd == MCASP_WRITE)
    {

    }
    else
    {

    }

}
Mcasp_HwSetupData mcaspRcvSetup = {
/* .rmask    = */0xFFFFFFFF,
                                    /* All the data bits are to be used     */

                                    /* .rfmt     = */0x000080b0,
                                    /* 0 bit delay from framsync
                                     * MSB first
                                     * No extra bit padding
                                     * Padding bit (ignore)
                                     * slot Size is 24
                                     * Reads from DMA port
                                     * NO rotation
                                     */

                                    /* .afsrctl  = */0x00000193, /* 3-slot TDM mode,
                                     * Frame sync is one word
                                     * Internally generated frame sync
                                     * Falling edge is start of frame
                                     */

                                    /* I2S MODE*/
                                    /* .rtdm     = */0x00000007, /* 3 slots are active
                                     *            */

                                    /* .rintctl  = */0x000000b3, /* sync error and overrun error         */
                                    /* .rstat    = */0x000001FF, /* reset any existing status bits       */
                                    /* .revtctl  = */0x00000000, /* DMA request is enabled or disabled   */
                                    { //25Mhz

        /* I2S MODE*/
        /* .aclkrctl  = */0x00000023, /* Div (4), Internal Source, rising edge */
        /* .ahclkrctl = */0x00008003, /* Div (4), Internal AUX_CLK Source */

        /* .rclkchk   = */0x00000000 } };

Mcasp_HwSetupData mcaspXmtSetup = {
/* .xmask    = */0xFFFFFFFF, /* All the data bits are to be used     */
                                    /* I2S MODE*/
                                    /* .xfmt     = */0x000080b0,  //0x4846 80A8
        /*
         * 0 bit delay from framsync
         * MSB first
         * No extra bit padding
         * Padding bit (ignore)
         * slot Size is 24
         * Reads from DMA port
         * 0-bit rotation
         */

        /*I2S MODE*/
        /* .afsxctl  = */0x00000193, /* 3-slot  TDM mode,//0x4846 80AC
         * Frame sync is one word
         * internally generated frame sync
         * Falling edge is start of frame
         */
        /* .xtdm     = */0x00000007, /* 3 slots are active  */  // 0x4846 80B8

        /* .xintctl  = */0x000000b7, /* sync error,overrun error,clK error   */ //0x4846 80BC
        /* .xstat    = */0x000001FF, /* reset any existing status bits       */ //0x4846 80C0
        /* .xevtctl  = */0x00000000, /* DMA request is enabled or disabled   */ //0x4846 80CC
        { //25Mhz

        /* I2S MODE*/ // 0x4846 80B0
        /* .aclkxctl  = */0x00000023, /* Div (4), Internal Source, SYNC, Falling edge */
        /* .ahclkxctl = */0x00008003, /* Div (4), Internal AUX_CLK Source */

        /* .xclkchk   = */0x00000000 },

};

/* The below variables are used to quit the frame processing loop if an error occurs */
int gblErrFlagXmt = 0;
int gblErrFlagRcv = 0;
/* The below variables are used to analyze the errors if an error interrupt happens */
Mcasp_errCbStatus errCbStatusXmt;
Mcasp_errCbStatus errCbStatusRcv;

/* Error handler for Transmit side */
void GblErrXmt(Mcasp_errCbStatus errCbStat)
{
    gblErrFlagXmt = 1;
    errCbStatusXmt = errCbStat;
    System_printf("GblErrXmt\n");
}
/* Error handler for Rcv side */
void GblErrRcv(Mcasp_errCbStatus errCbStat)
{
    gblErrFlagRcv = 1;
    errCbStatusRcv = errCbStat;
    System_printf("GblErrRcv\n");
}

Mcasp_Params mcaspParams;
Ptr hMcaspDev;
/* McAsp channel parameters                                  */
Mcasp_ChanParams mcasp_txchanparam = { //
        .noOfSerRequested = TX_NUM_SERIALIZER, //1
        .indexOfSersRequested = { Mcasp_SerializerNum_0 }, //
        .mcaspSetup = &mcaspXmtSetup, //
        .isDmaDriven = TRUE, .channelMode = Mcasp_OpMode_TDM, //
        .wordWidth = Mcasp_WordLength_24, //
        .userLoopJobBuffer = NULL, .userLoopJobLength = 0, //
        .edmaHandle = NULL, //
        .gblCbk = (Mcasp_GblCallback) &GblErrXmt, //
        .noOfChannels = 1, //
        .dataFormat = Mcasp_BufferFormat_1SER_MULTISLOT_NON_INTERLEAVED, //
        .enableHwFifo = TRUE, //
        .hwFifoEventDMARatio = TX_FIFO_EVENT_DMA_RATIO, //
        .isDataPacked = TRUE, //
        .wordBitsSelect = Mcasp_WordBitsSelect_LSB //
        };
Mcasp_ChanParams mcasp_rxchanparam = { //
        .noOfSerRequested = RX_NUM_SERIALIZER, //1
        .indexOfSersRequested = { Mcasp_SerializerNum_1 }, //
        .mcaspSetup = &mcaspRcvSetup, //
        .isDmaDriven = TRUE, //
        .channelMode = Mcasp_OpMode_TDM, //
        .wordWidth = Mcasp_WordLength_24, //
        .userLoopJobBuffer = NULL, //
        .userLoopJobLength = 0, //
        .edmaHandle = NULL, //
        .gblCbk = (Mcasp_GblCallback) &GblErrRcv, //
        .noOfChannels = 1, //
        .dataFormat = Mcasp_BufferFormat_1SER_MULTISLOT_NON_INTERLEAVED, //
        .enableHwFifo = TRUE, //
        .hwFifoEventDMARatio = RX_FIFO_EVENT_DMA_RATIO, //
        .isDataPacked = TRUE, //
        .wordBitsSelect = Mcasp_WordBitsSelect_LSB //
        };
/* Channel Handles */
Ptr hMcaspTxChan;
Ptr hMcaspRxChan;
/**************************************************************************************/
/*   FUNCTION DESCRIPTION: This utility function converts local GEM L2 address in to global
 memory addresses used by the EDMA inside McASP
 */
/**************************************************************************************/
static uintptr_t getGlobalAddr(uintptr_t addr)
{
    if ((addr >= 0x800000) && (addr < 0x1000000))
    {
#ifdef _TMS320C6X
        uint32_t coreNum;

        /* Get the core number. */
        coreNum = CSL_chipReadReg(CSL_CHIP_DNUM);

#if defined(SOC_AM572x) || defined(SOC_AM571x)
        /* Compute the global address. */
        return ((1 << 30) | (coreNum << 24) | (addr & 0x00ffffff));

#else
  /* Compute the global address. */
        return ((1 << 28) | (coreNum << 24) | (addr & 0x00ffffff));
#endif
#else
        return addr;
#endif
    }
    else
    {
        /* non-L2 address range */
        return addr;
    }
}
/*
 * ======== prime ========
 */
MCASP_Packet rxFrame;
MCASP_Packet txFrame;
#pragma DATA_SECTION (rxbuf,".l2sram")
#pragma DATA_ALIGN (rxbuf,128)
uint8_t rxbuf[100];
#pragma DATA_SECTION (txbuf,".l2sram")
#pragma DATA_ALIGN (txbuf,128)
uint8_t txbuf[100];
Void mcasp_test_Task(void)
{
    Mcasp_HwInfo hwInfo;
    volatile int32_t i32Count, status = 0;
    int32_t count = 0;

    Mcasp_socGetInitCfg(MCASP_NUM, &hwInfo);

    hwInfo.dmaHandle = McaspApp_edmaInit(&hwInfo);

    Mcasp_socSetInitCfg(MCASP_NUM, &hwInfo);
    mcaspParams = Mcasp_PARAMS;
    mcaspParams.mcaspHwSetup.glb.dlbMode = (CSL_MCASP_DLBCTL_DLBEN_ENABLE
            | ( CSL_MCASP_DLBCTL_ORD_XMTEVEN << CSL_MCASP_DLBCTL_ORD_SHIFT)
            | ( CSL_MCASP_DLBCTL_MODE_XMTCLK << CSL_MCASP_DLBCTL_MODE_SHIFT));

    status = mcaspBindDev(&hMcaspDev, MCASP_NUM, &mcaspParams);
    if ((status != MCASP_COMPLETED) || (hMcaspDev == NULL))
    {
        System_printf("mcaspBindDev for McASP Failed\n");
//        abort();
    }
    else
    {
        System_printf("mcaspBindDev for McASP success\n");
    }

    /* Create Mcasp channel for Tx */
    status = mcaspCreateChan(&hMcaspTxChan, hMcaspDev, MCASP_OUTPUT,
                             &mcasp_txchanparam, mcaspAppCallback, NULL);
    if ((status != MCASP_COMPLETED) || (hMcaspTxChan == NULL))
    {
        System_printf("mcaspCreateChan for McASP3 Tx Failed %d\n", status);
//        BIOS_exit(0);
    }
    else
    {
        System_printf("mcaspCreateChan for McASP3 Tx success\n");
    }

    /* Create Mcasp channel for Rx */
    status = mcaspCreateChan(&hMcaspRxChan, hMcaspDev, MCASP_INPUT,
                             &mcasp_rxchanparam, mcaspAppCallback, NULL);
    if ((status != MCASP_COMPLETED) || (hMcaspRxChan == NULL))
    {
        System_printf("mcaspCreateChan for McASP3 Rx Failed\n");
//        BIOS_exit(0);
    }
    else
    {
        System_printf("mcaspCreateChan for McASP3 Rx success\n");
    }
    uint32_t tx_bytes_per_sample = (mcasp_txchanparam.wordWidth / 8);
    uint32_t rx_bytes_per_sample = (mcasp_rxchanparam.wordWidth / 8);
    uint32_t tx_frame_size = mcasp_txchanparam.noOfSerRequested
            * tx_bytes_per_sample;
    uint32_t rx_frame_size = mcasp_rxchanparam.noOfSerRequested
            * rx_bytes_per_sample;
    System_printf("rx_frame_size:%d,tx_frame_size:%d\n", rx_frame_size,
                  tx_frame_size);
//    rxbuf = malloc(rx_frame_size);
//    txbuf = malloc(tx_frame_size);
    memset(rxbuf, 0, rx_frame_size);
    memset(txbuf, 3, tx_frame_size);

    rxFrame.cmd = MCASP_READ;
    rxFrame.addr = rxbuf; //(void*)(getGlobalAddr((uintptr_t) rxbuf));
    rxFrame.size = rx_frame_size;
    rxFrame.arg = (uintptr_t) hMcaspRxChan;
    rxFrame.status = 0;
    rxFrame.misc = 1; /* reserved - used in callback to indicate asynch packet */

    status = mcaspSubmitChan(hMcaspRxChan, &rxFrame);
    if ((status != MCASP_PENDING))
    {
        System_printf(
                "Debug: Error McASP3 RX : Prime  buffer  #%d submission FAILED\n",
                status);
    }
    else
    {
        System_printf(
                "Debug:  McASP3 RX : Prime  buffer  #%d submission Success\n",
                status);
    }

    txFrame.cmd = MCASP_WRITE;
    txFrame.addr = txbuf; //(void*) (getGlobalAddr((uintptr_t) txbuf));
    txFrame.size = tx_frame_size;
    txFrame.arg = (uintptr_t) hMcaspTxChan;
    txFrame.status = 0;
    txFrame.misc = 1; /* reserved - used in callback to indicate asynch packet */

    status = mcaspSubmitChan(hMcaspTxChan, &txFrame);
    if ((status != MCASP_PENDING))
    {
        System_printf(
                "Debug: Error McASP3 TX : Prime  buffer  #%d submission FAILED\n",
                status);
    }
    else
    {
        System_printf(
                "Debug:  McASP3 TX : Prime  buffer  #%d submission Success\n",
                status);
    }

    Task_sleep(1000);
    int cnt = 0;
    for (cnt = 0; cnt < tx_frame_size; cnt++)
    {
        System_printf("txbuf[%d]:%d,rxbuf[%d]:%d\r\n", cnt, txbuf[cnt], cnt,
                      rxbuf[cnt]);
    }

    status = McASPTxStatusGet(CSL_MPU_MCASP3_CFG_REGS); //0x4846 80c0
    System_printf("Txstatus:%x\r\n", status);
    status = McASPRxStatusGet(CSL_MPU_MCASP3_CFG_REGS); //0x4846 8080
    System_printf("Rxstatus:%x\r\n", status);
//
//    status = mcaspControlChan(hMcaspRxChan, Mcasp_IOCTL_CHAN_PARAMS_WORD_WIDTH,
//                              &mcasp_chanparam[0]);
    status = mcaspDeleteChan(hMcaspRxChan);
    System_printf("Deleting Rx channel %d\r\n", status);
    status = mcaspDeleteChan(hMcaspTxChan);
    System_printf("Deleting Tx channel %d\r\n", status);
    status = mcaspUnBindDev(hMcaspDev);
    System_printf("UnBinding Mcasp %d\r\n", status);
}
void McASP3_Enable(void)
{

    //uint32_t regVal = 0U;

        // Choose SYS_CLK2 (22.5792 MHZ) as source for ABE_PLL REF CLK
        HW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG, \
                CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG_CLKSEL, \
                CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG_CLKSEL_SEL_SYS_CLK1);

        /* Reprogram ABE DPLL for 451.584 MHz output on PER_ABE_X1_GFCLK line */

        // step 1: disable the PLL, if enabled (ex: via GEL)
        while(HW_RD_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG, \
                CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN) == CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE)
            HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG, \
                    CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN, \
                    CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_FR_BYP_MODE);

        // step 2: modify Synthesized Clock Parameters - DPLL MULT & DIV
        HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG, \
                CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG_DPLL_MULT, \
                0xC8);

        HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG, \
                CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG_DPLL_DIV, \
                0x09);

        // step 3: Configure output clocks parameters - M2 = 1  M3 = 1
        HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_ABE_REG, \
                CSL_CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_ABE_REG_DIVHS, \
                0x1);
        HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_ABE_REG, \
                CSL_CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_ABE_REG_DIVHS, \
                0x1);

        // step 4: Confirm that the PLL has locked
        while(HW_RD_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG, \
                CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN) != CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE)
            HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG, \
                    CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN, \
                    CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE);

        /* McASP3 Module Control */
        HW_WR_FIELD32(CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG, \
                CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG_MODULEMODE, \
                CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG_MODULEMODE_ENABLE);
        while ((HW_RD_REG32(CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG) & CM_L4PER2_MCASP3_CLKCTRL_MODULEMODE_MASK) != \
                CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG_MODULEMODE_ENABLE) ;


     /* PAD IO Config for McASP3 pins - ACLKX, AFSX, AXR0, AXR1*/
        HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_ACLKX, \
            CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_ACLKX_MCASP3_ACLKX_MUXMODE, \
            0xc0000);//0x4a00 3724
        HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_FSX, \
                CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_FSX_MCASP3_FSX_MUXMODE, \
                0xc0000);//0x4a00 3728
        HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR0, \
                CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR0_MCASP3_AXR0_MUXMODE, \
                0xc0000);//0x4a00 372c
        HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR1, \
                CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR1_MCASP3_AXR1_MUXMODE, \
                0xc0000);//0x4a00 3730

        //HW_WR_REG32(0x4AE06160, 0x1); // CM_CLKSEL_CLKOUT2: 0x1: Selects SYS_CLK2
        HW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG, \
                CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG_CLKSEL, \
                CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG_CLKSEL_SEL_SYS_CLK2);//0x4ae0 6160

        HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0, \
                CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0_XREF_CLK0_INPUTENABLE, \
                    0x0);   // 0x0: Receive mode is disabled

        HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0, \
                CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0_XREF_CLK0_MUXMODE, \
                0x9);   //0x9: clkout2  //0x4a00 3694


        HW_WR_FIELD32(CSL_DSP_COREAON_CM_CORE_REGS+CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG, \
                CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG_OPTFCLKEN_CLKOUTMUX2_CLK, \
                CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG_OPTFCLKEN_CLKOUTMUX2_CLK_FCLK_EN);//0x4a00 86b0


}
/***************************** End Of File ***********************************/

期待您的回复,感谢!

  • 请问测试的是以下链接中的哪个例程?

    software-dl.ti.com/.../index_device_drv.html

  • 感谢回复,我是用的例程是DeviceLoopback_ExampleProject。

  • 您好,这是使用例程的输出:

    1.021] Error waiting for packets!
    [ 1.021]
    [ 1.021] Total frames sent: 0
    [ 1.021] Total frames received: 0
    [ 1.021]
    [ 1.021] ******************* Transmit Watch dog stats ****************
    [ 1.021] ------------ Error stats --------------
    [ 1.021] ***** isClkFailErr : 0
    [ 1.021] ***** isDMAErr : 0
    [ 1.021] ***** isSyncErr : 0
    [ 1.021] ***** retVal : -1
    [ 1.021] ***** isRcvOvrRunOrTxUndRunErr : 1
    [ 1.021]
    [ 1.021]
    [ 1.021] ******************* Receive Watch dog stats ****************
    [ 1.021] ------------ Error stats --------------
    [ 1.021] ***** isClkFailErr : 1
    [ 1.021] ***** isDMAErr : 0
    [ 1.021] ***** isSyncErr : 0
    [ 1.021] ***** retVal : -1
    [ 1.021] ***** isRcvOvrRunOrTxUndRunErr : 0
    [ 1.021]
    [ 1.021] Deleting Rx channel
    [ 1.021] Deleting Tx channel
    [ 1.021] UnBinding Mcasp
    [ 1.021] TEST FAIL: Test quit after sending 0 frames and receiving 0 frames.
    [ 1.021]
    [ 1.021] TEST FAIL: Ramp test never found sync on rx for Serializer=0, timeslot=0
    [ 1.021]
    [ 1.021] TEST FAIL: Ramp test never found sync on rx for Serializer=0, timeslot=1
    [ 1.021]
    [ 1.021] TEST FAIL:Some tests have failed

  • 好的,我帮您升级到英文论坛,会有相关专家给你提供支持。

    e2e.ti.com/.../am5718-mcasp-loopback-failed

  • 好的  感谢帮助,那边没有回复,您能帮我滴一下吗?

  • 好的,请耐心等待。

  • 您好,我尝试在不调用任何MCASPAPI的情况下,只配置MCASP3的时钟,对MCASP_TXBUFn寄存器进行写入和读取,但是在写入后读取寄存器的值仍然为0,而这个寄存器是可读可写权限的,这令我实在是感到不可思议。

    测试方法如下:

    for(i = 0;i < 4;i++)
    {
        HW_WR_REG32(0x48468200+4*i, 0x123);
        uint32_t regVal = HW_RD_REG32(0x48468200+4*i);
        System_printf("HW_RD_REG32:0x%x\r\n", regVal);
        Task_sleep(1000);
    }

    测试结果如下:

    HW_RD_REG32:0x0

    HW_RD_REG32:0x0

    HW_RD_REG32:0x0

    HW_RD_REG32:0x0

    这是为什么呢?

    期待您的解答,谢谢!

  • 您好,我收集了测试程序日志结果如下:

    [ 725.226282] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
    [ 725.232193] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
    [ 725.240410] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
    [ 725.264981] omap_hwmod: mmu1_dsp1: _wait_target_disable failed
    [ 725.278081] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
    [ 725.285865] remoteproc remoteproc2: stopped remote processor 40800000.dsp
    [ 725.293926] remoteproc remoteproc2: releasing 40800000.dsp
    [ 725.299993] omap-rproc 40800000.dsp: assigned reserved memory node dsp1_cma@99000000
    [ 725.315241] remoteproc remoteproc2: 40800000.dsp is available
    [ 725.328306] remoteproc remoteproc2: powering up 40800000.dsp
    [ 725.341552] remoteproc remoteproc2: Booting fw image dra7-dsp1-fw.xe66, size 5876360
    [ 725.358015] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
    [ 725.363922] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
    [ 725.369916] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
    [ 725.394526] virtio_rpmsg_bus virtio1: rpmsg host is online
    [ 725.400078] remoteproc remoteproc2: registered virtio1 (type 7)
    [ 725.406077] omap-iommu 40d02000.mmu: iommu fault: da 0x46000000 flags 0x0
    [ 725.406084] remoteproc remoteproc2: crash detected in 40800000.dsp: type mmufault
    [ 725.406093] omap-iommu 40d02000.mmu: 40d02000.mmu: errs:0x00000002 da:0x46000000 pgd:0xd4361180 *pgd:px00000000
    [ 725.445954] remoteproc remoteproc2: remote processor 40800000.dsp is now up
    [ 725.455786] virtio_rpmsg_bus virtio1: creating channel rpmsg-proto addr 0x3d
    [ 725.465537] remoteproc remoteproc2: handling crash #1 in 40800000.dsp
    [ 725.477006] remoteproc remoteproc2: recovering 40800000.dsp
    [ 725.505384] omap_hwmod: mmu1_dsp1: _wait_target_disable failed
    [ 725.518459] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
    [ 725.529416] remoteproc remoteproc2: stopped remote processor 40800000.dsp
    [ 725.536379] remoteproc remoteproc2: powering up 40800000.dsp
    [ 725.551553] remoteproc remoteproc2: Booting fw image dra7-dsp1-fw.xe66, size 5876360
    [ 725.568137] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
    [ 725.574043] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
    [ 725.580027] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
    [ 725.604589] virtio_rpmsg_bus virtio1: rpmsg host is online
    [ 725.614004] remoteproc remoteproc2: registered virtio1 (type 7)
    [ 725.619962] omap-iommu 40d02000.mmu: iommu fault: da 0x46000000 flags 0x0
    [ 725.619968] remoteproc remoteproc2: crash detected in 40800000.dsp: type mmufault
    [ 725.619977] omap-iommu 40d02000.mmu: 40d02000.mmu: errs:0x00000002 da:0x46000000 pgd:0xed925180 *pgd:px00000000
    [ 725.658050] remoteproc remoteproc2: remote processor 40800000.dsp is now up
    [ 725.667794] virtio_rpmsg_bus virtio1: creating channel rpmsg-proto addr 0x3d

    似乎是有抢占资源的问题,您能帮我分析下原因吗?

    感谢!

  • 您好,我查询到这个remoteproc remoteproc2: crash detected in 40800000.dsp: type mmufault出现的原因是可能资源表没有配置正确,但是我按照手册配置过后输出结果依然是这样,是配置出了什么问题吗?

    config.bld如下:

    /*
     * Copyright (c) 2013-2015, Texas Instruments Incorporated
     * All rights reserved.
     *
     * Redistribution and use in source and binary forms, with or without
     * modification, are permitted provided that the following conditions
     * are met:
     *
     * *  Redistributions of source code must retain the above copyright
     *    notice, this list of conditions and the following disclaimer.
     *
     * *  Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the
     *    documentation and/or other materials provided with the distribution.
     *
     * *  Neither the name of Texas Instruments Incorporated nor the names of
     *    its contributors may be used to endorse or promote products derived
     *    from this software without specific prior written permission.
     *
     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     */
    
    /*
     *  ======== config.bld ========
     *
     */
    var Build = xdc.useModule('xdc.bld.BuildEnvironment');
    
    var evmDRA7XX_L2SRAM = {
            name: "DSPL2SRAM", space: "data", access: "RWX",
            base: 0x40808000, len: 0x40000,
            comment: "sram Memory (256 KB)"
    };
    
    var evmDRA7XX_EDMA = {
            name: "DSPEDMA", space: "data", access: "RWX",
            base: 0x43300000, len: 0x100000,
            comment: "edma Memory (1 MB)"
    };
    
    var evmDRA7XX_MCASP3 = {
            name: "DSPMCASP3", space: "data", access: "RWX",
            base: 0x46000000, len: 0x100000,
            comment: "MCASP3 Memory (1 MB)"
    };
    
    /*  Memory Map for ti.platforms.evmDRA7XX:dsp1 and ti.platforms.evmDRA7XX:dsp2
     *
     *  --- External Memory ---
     *  Virtual     Physical        Size            Comment
     *  ------------------------------------------------------------------------
     *  9500_4000   ????_????    10_0000  (  ~1 MB) EXT_CODE
     *  9510_0000   ????_????    10_0000  (   1 MB) EXT_DATA
     *  9520_0000   ????_????    30_0000  (   3 MB) EXT_HEAP
     *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
     *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
     *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
     */
    var evmDRA7XX_ExtMemMapDsp = {
        EXT_CODE: {
            name: "EXT_CODE",
            base: 0x95000000,
            len:  0x00100000,
            space: "code",
            access: "RWX"
        },
        EXT_DATA: {
            name: "EXT_DATA",
            base: 0x95100000,
            len:  0x00100000,
            space: "data",
            access: "RW"
        },
        EXT_HEAP: {
            name: "EXT_HEAP",
            base: 0x95200000,
            len:  0x00300000,
            space: "data",
            access: "RW"
        },
        TRACE_BUF: {
            name: "TRACE_BUF",
            base: 0x9F000000,
            len:  0x00060000,
            space: "data",
            access: "RW"
        },
        EXC_DATA: {
            name: "EXC_DATA",
            base: 0x9F060000,
            len:  0x00010000,
            space: "data",
            access: "RW"
        },
        PM_DATA: {
            name: "PM_DATA",
            base: 0x9F070000,
            len:  0x00020000,
            space: "data",
            access: "RWX"  /* should this have execute perm? */
        },
        DSP_L2SRAM: {
            name: evmDRA7XX_L2SRAM.name,
            base: evmDRA7XX_L2SRAM.base,
            len:  evmDRA7XX_L2SRAM.len,
            space: "data",
            access: "RW"
        },
        DSP_EDMA: {
            name: evmDRA7XX_EDMA.name,
            base: evmDRA7XX_EDMA.base,
            len:  evmDRA7XX_EDMA.len,
            space: "data",
            access: "RW"
        },
        DSP_MCASP3: {
            name: evmDRA7XX_MCASP3.name,
            base: evmDRA7XX_MCASP3.base,
            len:  evmDRA7XX_MCASP3.len,
            space: "data",
            access: "RW"
        },
    };
    
    Build.platformTable["ti.platforms.evmDRA7XX:dsp1"] = {
        externalMemoryMap: [
            [ "EXT_CODE", evmDRA7XX_ExtMemMapDsp.EXT_CODE ],
            [ "EXT_DATA", evmDRA7XX_ExtMemMapDsp.EXT_DATA ],
            [ "EXT_HEAP", evmDRA7XX_ExtMemMapDsp.EXT_HEAP ],
            [ "TRACE_BUF", evmDRA7XX_ExtMemMapDsp.TRACE_BUF ],
            [ "EXC_DATA", evmDRA7XX_ExtMemMapDsp.EXC_DATA ],
            [ "PM_DATA", evmDRA7XX_ExtMemMapDsp.PM_DATA ],
            [ evmDRA7XX_L2SRAM.name, evmDRA7XX_ExtMemMapDsp.DSP_L2SRAM ],
            [ evmDRA7XX_EDMA.name, evmDRA7XX_ExtMemMapDsp.DSP_EDMA ],
            [ evmDRA7XX_MCASP3.name, evmDRA7XX_ExtMemMapDsp.DSP_MCASP3 ],
        ],
        codeMemory: "EXT_CODE",
        dataMemory: "EXT_DATA",
        stackMemory: "EXT_DATA",
    };
    Build.platformTable["ti.platforms.evmDRA7XX:dsp2"] =
    	Build.platformTable["ti.platforms.evmDRA7XX:dsp1"];
    
    
    /*  Memory Map for ti.platforms.evmDRA7XX:ipu2
     *
     *  --- External Memory ---
     *  Virtual     Physical        Size            Comment
     *  ------------------------------------------------------------------------
     *  0000_4000   ????_????    5F_C000  (  ~6 MB) EXT_CODE
     *  8000_0000   ????_????    60_0000  (   6 MB) EXT_DATA
     *  8060_0000   ????_????   960_0000  (  86 MB) EXT_HEAP
     *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
     *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
     *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
     */
    var evmDRA7XX_ExtMemMapIpu2 = {
        EXT_CODE: {
            name: "EXT_CODE",
            base: 0x00004000,
            len:  0x005FC000,
            space: "code",
            access: "RWX"
        },
        EXT_DATA: {
            name: "EXT_DATA",
            base: 0x80000000,
            len:  0x00600000,
            space: "data",
            access: "RW"
        },
        EXT_HEAP: {
            name: "EXT_HEAP",
            base: 0x80600000,
            len:  0x09600000,
            space: "data",
            access: "RW"
        },
        TRACE_BUF: {
            name: "TRACE_BUF",
            base: 0x9F000000,
            len:  0x00060000,
            space: "data",
            access: "RW"
        },
        EXC_DATA: {
            name: "EXC_DATA",
            base: 0x9F060000,
            len:  0x00010000,
            space: "data",
            access: "RW"
        },
        PM_DATA: {
            name: "PM_DATA",
            base: 0x9F070000,
            len:  0x00020000,
            space: "data",
            access: "RWX"  /* should this have execute perm? */
        }
    };
    
    Build.platformTable["ti.platforms.evmDRA7XX:ipu2"] = {
        externalMemoryMap: [
            [ "EXT_CODE", evmDRA7XX_ExtMemMapIpu2.EXT_CODE ],
            [ "EXT_DATA", evmDRA7XX_ExtMemMapIpu2.EXT_DATA ],
            [ "EXT_HEAP", evmDRA7XX_ExtMemMapIpu2.EXT_HEAP ],
            [ "TRACE_BUF", evmDRA7XX_ExtMemMapIpu2.TRACE_BUF ],
            [ "EXC_DATA", evmDRA7XX_ExtMemMapIpu2.EXC_DATA ],
            [ "PM_DATA", evmDRA7XX_ExtMemMapIpu2.PM_DATA ]
        ],
        codeMemory: "EXT_CODE",
        dataMemory: "EXT_DATA",
        stackMemory: "EXT_DATA",
    };
    
    /*  Memory Map for ti.platforms.evmDRA7XX:ipu1
     *
     *  --- External Memory ---
     *  Virtual     Physical        Size            Comment
     *  ------------------------------------------------------------------------
     *  0000_4000   ????_????     F_C000  (  ~1 MB) EXT_CODE
     *  8000_0000   ????_????    20_0000  (   2 MB) EXT_DATA
     *  8020_0000   ????_????    30_0000  (   3 MB) EXT_HEAP
     *  9F00_0000   9F00_0000     6_0000  ( 384 kB) TRACE_BUF
     *  9F06_0000   9F06_0000     1_0000  (  64 kB) EXC_DATA
     *  9F07_0000   9F07_0000     2_0000  ( 128 kB) PM_DATA (Power mgmt)
     */
    var evmDRA7XX_ExtMemMapIpu1 = {
        EXT_CODE: {
            name: "EXT_CODE",
            base: 0x00004000,
            len:  0x000FC000,
            space: "code",
            access: "RWX"
        },
        EXT_DATA: {
            name: "EXT_DATA",
            base: 0x80000000,
            len:  0x00200000,
            space: "data",
            access: "RW"
        },
        EXT_HEAP: {
            name: "EXT_HEAP",
            base: 0x80200000,
            len:  0x00300000,
            space: "data",
            access: "RW"
        },
        TRACE_BUF: {
            name: "TRACE_BUF",
            base: 0x9F000000,
            len:  0x00060000,
            space: "data",
            access: "RW"
        },
        EXC_DATA: {
            name: "EXC_DATA",
            base: 0x9F060000,
            len:  0x00010000,
            space: "data",
            access: "RW"
        },
        PM_DATA: {
            name: "PM_DATA",
            base: 0x9F070000,
            len:  0x00020000,
            space: "data",
            access: "RWX"  /* should this have execute perm? */
        }
    };
    
    Build.platformTable["ti.platforms.evmDRA7XX:ipu1"] = {
        externalMemoryMap: [
            [ "EXT_CODE", evmDRA7XX_ExtMemMapIpu1.EXT_CODE ],
            [ "EXT_DATA", evmDRA7XX_ExtMemMapIpu1.EXT_DATA ],
            [ "EXT_HEAP", evmDRA7XX_ExtMemMapIpu1.EXT_HEAP ],
            [ "TRACE_BUF", evmDRA7XX_ExtMemMapIpu1.TRACE_BUF ],
            [ "EXC_DATA", evmDRA7XX_ExtMemMapIpu1.EXC_DATA ],
            [ "PM_DATA", evmDRA7XX_ExtMemMapIpu1.PM_DATA ]
        ],
        codeMemory: "EXT_CODE",
        dataMemory: "EXT_DATA",
        stackMemory: "EXT_DATA",
    };

    资源表配置如下:

    /*
     * Copyright (c) 2017, Texas Instruments Incorporated
     * All rights reserved.
     *
     * Redistribution and use in source and binary forms, with or without
     * modification, are permitted provided that the following conditions
     * are met:
     *
     * *  Redistributions of source code must retain the above copyright
     *    notice, this list of conditions and the following disclaimer.
     *
     * *  Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the
     *    documentation and/or other materials provided with the distribution.
     *
     * *  Neither the name of Texas Instruments Incorporated nor the names of
     *    its contributors may be used to endorse or promote products derived
     *    from this software without specific prior written permission.
     *
     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     */
    
    /*
     *  ======== rsc_table_dsp.h ========
     *
     *  Define the resource table entries for all DSP cores. This will be
     *  incorporated into corresponding base images, and used by the remoteproc
     *  on the host-side to allocated/reserve resources.
     *
     */
    
    #ifndef _RSC_TABLE_DSP_H_
    #define _RSC_TABLE_DSP_H_
    
    #include <ti/ipc/remoteproc/rsc_types.h>
    
    /* DSP Memory Map */
    #define L4_DRA7XX_BASE          0x4A000000
    
    #define L4_PERIPHERAL_L4CFG     (L4_DRA7XX_BASE)
    #define DSP_PERIPHERAL_L4CFG    0x4A000000
    
    #define L4_PERIPHERAL_L4PER1    0x48000000
    #define DSP_PERIPHERAL_L4PER1   0x48000000
    
    #define L4_PERIPHERAL_L4PER2    0x48400000
    #define DSP_PERIPHERAL_L4PER2   0x48400000
    
    #define L4_PERIPHERAL_L4PER3    0x48800000
    #define DSP_PERIPHERAL_L4PER3   0x48800000
    
    #define L4_PERIPHERAL_L4EMU     0x54000000
    #define DSP_PERIPHERAL_L4EMU    0x54000000
    
    #define L3_PERIPHERAL_DMM       0x4E000000
    #define DSP_PERIPHERAL_DMM      0x4E000000
    
    #define L3_TILER_MODE_0_1       0x60000000
    #define DSP_TILER_MODE_0_1      0x60000000
    
    #define L3_TILER_MODE_2         0x70000000
    #define DSP_TILER_MODE_2        0x70000000
    
    #define L3_TILER_MODE_3         0x78000000
    #define DSP_TILER_MODE_3        0x78000000
    
    #define L3_PERIPHERAL_EDMA_TPCC     0x43300000
    #define DSP_PERIPHERAL_EDMA_TPCC    0x43300000
    
    //#define L3_PERIPHERAL_EDMA_TPCC 0x40D05000
    //#define DSP_PERIPHERAL_EDMA_TPCC 0x40D05000
    
    #define DSP_PERIPHERAL_EDMA_SIZE  SZ_1M
    
    #define L3_PERIPHERAL_MCASP 0x46000000
    #define DSP_PERIPHERAL_MCASP 0x46000000
    
    #define DSP_PERIPHERAL_MCASP_SIZE  SZ_1M
    
    #define DSP_MEM_TEXT            0x95000000
    /* Co-locate alongside TILER region for easier flushing */
    #define DSP_MEM_IOBUFS          0x80000000
    #define DSP_MEM_DATA            0x95100000
    #define DSP_MEM_HEAP            0x95200000
    
    #define DSP_MEM_IPC_DATA        0x9F000000
    #define DSP_MEM_IPC_VRING       0x99000000
    #define DSP_MEM_RPMSG_VRING0    0x99000000
    #define DSP_MEM_RPMSG_VRING1    0x99004000
    #define DSP_MEM_VRING_BUFS0     0x99040000
    #define DSP_MEM_VRING_BUFS1     0x99080000
    
    #define DSP_MEM_IPC_VRING_SIZE  SZ_1M
    #define DSP_MEM_IPC_DATA_SIZE   SZ_1M
    #define DSP_MEM_TEXT_SIZE       SZ_1M
    #define DSP_MEM_DATA_SIZE       SZ_1M
    #define DSP_MEM_HEAP_SIZE       (SZ_1M * 3)
    #define DSP_MEM_IOBUFS_SIZE     (SZ_1M * 90)
    
    /* NOTE: Make sure this matches what is configured in the linux device tree */
    #define DSP_CMEM_IOBUFS 0xA0000000
    #define PHYS_CMEM_IOBUFS 0xA0000000
    #define DSP_CMEM_IOBUFS_SIZE (SZ_1M * 192)
    
    #define L2_RAM_BASE 0x40808000
    #define DSP_L2_RAM_BASE 0x40808000
    #define DSP_L2_RAM_SIZE 0x40000
    
    /*
     * Assign fixed RAM addresses to facilitate a fixed MMU table.
     */
    
    #define VAYU_DSP_1
    
    /* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
    #if defined (VAYU_DSP_1)
    #define PHYS_MEM_IPC_VRING      0x99000000
    #elif defined (VAYU_DSP_2)
    #define PHYS_MEM_IPC_VRING      0x9F000000
    #endif
    
    /* Need to be identical to that of IPU */
    #define PHYS_MEM_IOBUFS         0xBA300000
    
    /*
     * Sizes of the virtqueues (expressed in number of buffers supported,
     * and must be power of 2)
     */
    #define DSP_RPMSG_VQ0_SIZE      256
    #define DSP_RPMSG_VQ1_SIZE      256
    
    /* flip up bits whose indices represent features we support */
    #define RPMSG_DSP_C0_FEATURES         1
    
    struct my_resource_table {
        struct resource_table base;
    
        UInt32 offset[18];  /* Should match 'num' in actual definition */
    
        /* rpmsg vdev entry */
        struct fw_rsc_vdev rpmsg_vdev;
        struct fw_rsc_vdev_vring rpmsg_vring0;
        struct fw_rsc_vdev_vring rpmsg_vring1;
    
        /* text carveout entry */
        struct fw_rsc_carveout text_cout;
    
        /* data carveout entry */
        struct fw_rsc_carveout data_cout;
    
        /* heap carveout entry */
        struct fw_rsc_carveout heap_cout;
    
        /* ipcdata carveout entry */
        struct fw_rsc_carveout ipcdata_cout;
    
        /* trace entry */
        struct fw_rsc_trace trace;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem0;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem1;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem2;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem3;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem4;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem5;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem6;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem7;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem8;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem9;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem10;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem11;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem12;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem13;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem14;
    };
    
    extern char ti_trace_SysMin_Module_State_0_outbuf__A;
    #define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
    
    #pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
    #pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
    
    struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
        1,      /* we're the first version that implements this */
        18,     /* number of entries in the table */
        0, 0,   /* reserved, must be zero */
        /* offsets to entries */
        {
            offsetof(struct my_resource_table, rpmsg_vdev),
            offsetof(struct my_resource_table, text_cout),
            offsetof(struct my_resource_table, data_cout),
            offsetof(struct my_resource_table, heap_cout),
            offsetof(struct my_resource_table, ipcdata_cout),
            offsetof(struct my_resource_table, trace),
            offsetof(struct my_resource_table, devmem0),
            offsetof(struct my_resource_table, devmem1),
            offsetof(struct my_resource_table, devmem2),
            offsetof(struct my_resource_table, devmem3),
            offsetof(struct my_resource_table, devmem4),
            offsetof(struct my_resource_table, devmem5),
            offsetof(struct my_resource_table, devmem6),
            offsetof(struct my_resource_table, devmem7),
            offsetof(struct my_resource_table, devmem8),
            offsetof(struct my_resource_table, devmem9),
            offsetof(struct my_resource_table, devmem10),
            offsetof(struct my_resource_table, devmem11),
            offsetof(struct my_resource_table, devmem12),
            offsetof(struct my_resource_table, devmem13),
            offsetof(struct my_resource_table, devmem14),
        },
    
        /* rpmsg vdev entry */
        {
            TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
            RPMSG_DSP_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
            /* no config data */
        },
        /* the two vrings */
        { DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },
        { DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },
    
        {
            TYPE_CARVEOUT,
            DSP_MEM_TEXT, 0,
            DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT",
        },
    
        {
            TYPE_CARVEOUT,
            DSP_MEM_DATA, 0,
            DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",
        },
    
        {
            TYPE_CARVEOUT,
            DSP_MEM_HEAP, 0,
            DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",
        },
    
        {
            TYPE_CARVEOUT,
            DSP_MEM_IPC_DATA, 0,
            DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
        },
    
        {
            TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp",
        },
    
        {
            TYPE_DEVMEM,
            DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
            DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
        },
    
        {
            TYPE_DEVMEM,
            DSP_MEM_IOBUFS, PHYS_MEM_IOBUFS,
            DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
        },
    
        {
            TYPE_DEVMEM,
            DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,
            SZ_256M, 0, 0, "DSP_TILER_MODE_0_1",
        },
    
        {
            TYPE_DEVMEM,
            DSP_TILER_MODE_2, L3_TILER_MODE_2,
            SZ_128M, 0, 0, "DSP_TILER_MODE_2",
        },
    
        {
            TYPE_DEVMEM,
            DSP_TILER_MODE_3, L3_TILER_MODE_3,
            SZ_128M, 0, 0, "DSP_TILER_MODE_3",
        },
    
        {
            TYPE_DEVMEM,
            DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
            SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG",
        },
    
        {
            TYPE_DEVMEM,
            DSP_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
            SZ_2M, 0, 0, "DSP_PERIPHERAL_L4PER1",
        },
    
        {
            TYPE_DEVMEM,
            DSP_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
            SZ_4M, 0, 0, "DSP_PERIPHERAL_L4PER2",
        },
    
        {
            TYPE_DEVMEM,
            DSP_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
            SZ_8M, 0, 0, "DSP_PERIPHERAL_L4PER3",
        },
    
        {
            TYPE_DEVMEM,
            DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
            SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
        },
    
        {
            TYPE_DEVMEM,
            DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
            SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
        },
    
        {
            TYPE_DEVMEM,
            DSP_CMEM_IOBUFS, PHYS_CMEM_IOBUFS,
            DSP_CMEM_IOBUFS_SIZE, 0, 0, "DSP_CMEM_IOBUFS",
        },
    
        {
                TYPE_DEVMEM,
                DSP_L2_RAM_BASE,L2_RAM_BASE,
                DSP_L2_RAM_SIZE, 0, 0, "DSP_L2_RAM_BASE",
        },
        {
                TYPE_DEVMEM,
                DSP_PERIPHERAL_EDMA_TPCC, L3_PERIPHERAL_EDMA_TPCC,
                DSP_PERIPHERAL_EDMA_SIZE, 0, 0, "DSP_PERIPHERAL_EDMA_TPCC",
        },
        {
                TYPE_DEVMEM,
                L3_PERIPHERAL_MCASP, L3_PERIPHERAL_MCASP,
                DSP_PERIPHERAL_EDMA_SIZE, 0, 0, "DSP_MCASP",
        },
    };
    
    #endif /* _RSC_TABLE_DSP_H_ */

    感谢!

  • 您好,我将资源表修改后不再出现mmufault,TXTSTAT的值为0x50,但RXSTAT的值仍然为0x154出错状态,资源表如下:

    /*
     * Copyright (c) 2017, Texas Instruments Incorporated
     * All rights reserved.
     *
     * Redistribution and use in source and binary forms, with or without
     * modification, are permitted provided that the following conditions
     * are met:
     *
     * *  Redistributions of source code must retain the above copyright
     *    notice, this list of conditions and the following disclaimer.
     *
     * *  Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the
     *    documentation and/or other materials provided with the distribution.
     *
     * *  Neither the name of Texas Instruments Incorporated nor the names of
     *    its contributors may be used to endorse or promote products derived
     *    from this software without specific prior written permission.
     *
     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     */
    
    /*
     *  ======== rsc_table_dsp.h ========
     *
     *  Define the resource table entries for all DSP cores. This will be
     *  incorporated into corresponding base images, and used by the remoteproc
     *  on the host-side to allocated/reserve resources.
     *
     */
    
    #ifndef _RSC_TABLE_DSP_H_
    #define _RSC_TABLE_DSP_H_
    
    #include <ti/ipc/remoteproc/rsc_types.h>
    
    /* DSP Memory Map */
    #define L4_DRA7XX_BASE          0x4A000000
    
    #define L4_PERIPHERAL_L4CFG     (L4_DRA7XX_BASE)
    #define DSP_PERIPHERAL_L4CFG    0x4A000000
    
    #define L4_PERIPHERAL_L4PER1    0x48000000
    #define DSP_PERIPHERAL_L4PER1   0x48000000
    
    #define L4_PERIPHERAL_L4PER2    0x48400000
    #define DSP_PERIPHERAL_L4PER2   0x48400000
    
    #define L4_PERIPHERAL_L4PER3    0x48800000
    #define DSP_PERIPHERAL_L4PER3   0x48800000
    
    #define L4_PERIPHERAL_L4EMU     0x54000000
    #define DSP_PERIPHERAL_L4EMU    0x54000000
    
    #define L3_PERIPHERAL_DMM       0x4E000000
    #define DSP_PERIPHERAL_DMM      0x4E000000
    
    #define L3_TILER_MODE_0_1       0x60000000
    #define DSP_TILER_MODE_0_1      0x60000000
    
    #define L3_TILER_MODE_2         0x70000000
    #define DSP_TILER_MODE_2        0x70000000
    
    #define L3_TILER_MODE_3         0x78000000
    #define DSP_TILER_MODE_3        0x78000000
    
    #define L3_PERIPHERAL_EDMA_TPCC     0x43300000
    #define DSP_PERIPHERAL_EDMA_TPCC    0x43300000
    
    //#define L3_PERIPHERAL_EDMA_TPCC 0x40D05000
    //#define DSP_PERIPHERAL_EDMA_TPCC 0x40D05000
    
    #define DSP_PERIPHERAL_EDMA_SIZE  SZ_1M
    
    #define L3_PERIPHERAL_MCASP 0x46000000
    #define DSP_PERIPHERAL_MCASP 0x46000000
    
    #define DSP_PERIPHERAL_MCASP_SIZE  SZ_1M
    
    #define DSP_MEM_TEXT            0x95000000
    /* Co-locate alongside TILER region for easier flushing */
    #define DSP_MEM_IOBUFS          0x80000000
    #define DSP_MEM_DATA            0x95100000
    #define DSP_MEM_HEAP            0x95200000
    
    #define DSP_MEM_IPC_DATA        0x9F000000
    #define DSP_MEM_IPC_VRING       0x99000000
    #define DSP_MEM_RPMSG_VRING0    0x99000000
    #define DSP_MEM_RPMSG_VRING1    0x99004000
    #define DSP_MEM_VRING_BUFS0     0x99040000
    #define DSP_MEM_VRING_BUFS1     0x99080000
    
    #define DSP_MEM_IPC_VRING_SIZE  SZ_1M
    #define DSP_MEM_IPC_DATA_SIZE   SZ_1M
    #define DSP_MEM_TEXT_SIZE       SZ_1M
    #define DSP_MEM_DATA_SIZE       SZ_1M
    #define DSP_MEM_HEAP_SIZE       (SZ_1M * 3)
    #define DSP_MEM_IOBUFS_SIZE     (SZ_1M * 90)
    
    /* NOTE: Make sure this matches what is configured in the linux device tree */
    #define DSP_CMEM_IOBUFS 0xA0000000
    #define PHYS_CMEM_IOBUFS 0xA0000000
    #define DSP_CMEM_IOBUFS_SIZE (SZ_1M * 192)
    
    #define L2_RAM_BASE 0x40808000
    #define DSP_L2_RAM_BASE 0x40808000
    #define DSP_L2_RAM_SIZE 0x40000
    
    /*
     * Assign fixed RAM addresses to facilitate a fixed MMU table.
     */
    
    #define VAYU_DSP_1
    
    /* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
    #if defined (VAYU_DSP_1)
    #define PHYS_MEM_IPC_VRING      0x99000000
    #elif defined (VAYU_DSP_2)
    #define PHYS_MEM_IPC_VRING      0x9F000000
    #endif
    
    /* Need to be identical to that of IPU */
    #define PHYS_MEM_IOBUFS         0xBA300000
    
    /*
     * Sizes of the virtqueues (expressed in number of buffers supported,
     * and must be power of 2)
     */
    #define DSP_RPMSG_VQ0_SIZE      256
    #define DSP_RPMSG_VQ1_SIZE      256
    
    /* flip up bits whose indices represent features we support */
    #define RPMSG_DSP_C0_FEATURES         1
    
    struct my_resource_table {
        struct resource_table base;
    
        UInt32 offset[21];  /* Should match 'num' in actual definition */
    
        /* rpmsg vdev entry */
        struct fw_rsc_vdev rpmsg_vdev;
        struct fw_rsc_vdev_vring rpmsg_vring0;
        struct fw_rsc_vdev_vring rpmsg_vring1;
    
        /* text carveout entry */
        struct fw_rsc_carveout text_cout;
    
        /* data carveout entry */
        struct fw_rsc_carveout data_cout;
    
        /* heap carveout entry */
        struct fw_rsc_carveout heap_cout;
    
        /* ipcdata carveout entry */
        struct fw_rsc_carveout ipcdata_cout;
    
        /* trace entry */
        struct fw_rsc_trace trace;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem0;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem1;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem2;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem3;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem4;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem5;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem6;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem7;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem8;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem9;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem10;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem11;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem12;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem13;
    
        /* devmem entry */
        struct fw_rsc_devmem devmem14;
    };
    
    extern char ti_trace_SysMin_Module_State_0_outbuf__A;
    #define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
    
    #pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
    #pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
    
    struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
        1,      /* we're the first version that implements this */
        21,     /* number of entries in the table */
        0, 0,   /* reserved, must be zero */
        /* offsets to entries */
        {
            offsetof(struct my_resource_table, rpmsg_vdev),
            offsetof(struct my_resource_table, text_cout),
            offsetof(struct my_resource_table, data_cout),
            offsetof(struct my_resource_table, heap_cout),
            offsetof(struct my_resource_table, ipcdata_cout),
            offsetof(struct my_resource_table, trace),
            offsetof(struct my_resource_table, devmem0),
            offsetof(struct my_resource_table, devmem1),
            offsetof(struct my_resource_table, devmem2),
            offsetof(struct my_resource_table, devmem3),
            offsetof(struct my_resource_table, devmem4),
            offsetof(struct my_resource_table, devmem5),
            offsetof(struct my_resource_table, devmem6),
            offsetof(struct my_resource_table, devmem7),
            offsetof(struct my_resource_table, devmem8),
            offsetof(struct my_resource_table, devmem9),
            offsetof(struct my_resource_table, devmem10),
            offsetof(struct my_resource_table, devmem11),
            offsetof(struct my_resource_table, devmem12),
            offsetof(struct my_resource_table, devmem13),
            offsetof(struct my_resource_table, devmem14),
        },
    
        /* rpmsg vdev entry */
        {
            TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
            RPMSG_DSP_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
            /* no config data */
        },
        /* the two vrings */
        { DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },
        { DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },
    
        {
            TYPE_CARVEOUT,
            DSP_MEM_TEXT, 0,
            DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT",
        },
    
        {
            TYPE_CARVEOUT,
            DSP_MEM_DATA, 0,
            DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",
        },
    
        {
            TYPE_CARVEOUT,
            DSP_MEM_HEAP, 0,
            DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",
        },
    
        {
            TYPE_CARVEOUT,
            DSP_MEM_IPC_DATA, 0,
            DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
        },
    
        {
            TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp",
        },
    
        {
            TYPE_DEVMEM,
            DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
            DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
        },
    
        {
            TYPE_DEVMEM,
            DSP_MEM_IOBUFS, PHYS_MEM_IOBUFS,
            DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
        },
    
        {
            TYPE_DEVMEM,
            DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,
            SZ_256M, 0, 0, "DSP_TILER_MODE_0_1",
        },
    
        {
            TYPE_DEVMEM,
            DSP_TILER_MODE_2, L3_TILER_MODE_2,
            SZ_128M, 0, 0, "DSP_TILER_MODE_2",
        },
    
        {
            TYPE_DEVMEM,
            DSP_TILER_MODE_3, L3_TILER_MODE_3,
            SZ_128M, 0, 0, "DSP_TILER_MODE_3",
        },
    
        {
            TYPE_DEVMEM,
            DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
            SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG",
        },
    
        {
            TYPE_DEVMEM,
            DSP_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
            SZ_2M, 0, 0, "DSP_PERIPHERAL_L4PER1",
        },
    
        {
            TYPE_DEVMEM,
            DSP_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
            SZ_4M, 0, 0, "DSP_PERIPHERAL_L4PER2",
        },
    
        {
            TYPE_DEVMEM,
            DSP_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
            SZ_8M, 0, 0, "DSP_PERIPHERAL_L4PER3",
        },
    
        {
            TYPE_DEVMEM,
            DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
            SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
        },
    
        {
            TYPE_DEVMEM,
            DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
            SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
        },
    
        {
            TYPE_DEVMEM,
            DSP_CMEM_IOBUFS, PHYS_CMEM_IOBUFS,
            DSP_CMEM_IOBUFS_SIZE, 0, 0, "DSP_CMEM_IOBUFS",
        },
    
        {
                TYPE_DEVMEM,
                DSP_L2_RAM_BASE,L2_RAM_BASE,
                DSP_L2_RAM_SIZE, 0, 0, "DSP_L2_RAM_BASE",
        },
        {
                TYPE_DEVMEM,
                DSP_PERIPHERAL_EDMA_TPCC, L3_PERIPHERAL_EDMA_TPCC,
                DSP_PERIPHERAL_EDMA_SIZE, 0, 0, "DSP_PERIPHERAL_EDMA_TPCC",
        },
        {
                TYPE_DEVMEM,
                L3_PERIPHERAL_MCASP, L3_PERIPHERAL_MCASP,
                DSP_PERIPHERAL_EDMA_SIZE, 0, 0, "DSP_MCASP",
        },
    };
    
    #endif /* _RSC_TABLE_DSP_H_ */
    

    您能告诉我一点解决问题的思路吗?

    感谢!

  • 您好,我通过修改寄存器初始化的配置,实现了STAT的值为0x50没有错误,但是在内部回环模式下接收buff里面数据仍然全是0,还缺少了什么配置吗?

    寄存器初始化配置如下:

    Mcasp_HwSetupData mcaspRcvSetup = {
            /* .rmask    = */0xFFFFFFFF,
            /* All the data bits are to be used     */
    
            /* .rfmt     = */0x000080b0,
            /* 0 bit delay from framsync
             * MSB first
             * No extra bit padding
             * Padding bit (ignore)
             * slot Size is 24
             * Reads from DMA port
             * NO rotation
             */
    
            /* .afsrctl  = */0x00000193, /* 3-slot TDM mode,
             * Frame sync is one word
             * Internally generated frame sync
             * Falling edge is start of frame
             */
    
            /* I2S MODE*/
            /* .rtdm     = */0x00000007, /* 3 slots are active
             *            */
    
            /* .rintctl  = */0x000000b3, /* sync error and overrun error         */
            /* .rstat    = */0x000001FF, /* reset any existing status bits       */
            /* .revtctl  = */0x00000000, /* DMA request is enabled or disabled   */
            
            { //25Mhz
    
                /* I2S MODE*/
                /* .aclkrctl  = */0x000000a0, /* Div (4), Internal Source, rising edge */
                /* .ahclkrctl = */0x00008000, /* Div (4), Internal AUX_CLK Source */
    
                /* .rclkchk   = */0x00ff0000 //0x4846 8088
            } 
    }; 
    
    Mcasp_HwSetupData mcaspXmtSetup = {
            /* .xmask    = */0xFFFFFFFF, /* All the data bits are to be used     */
            /* I2S MODE*/
            /* .xfmt     = */0x000080b0,  //0x4846 80A8
            /*
             * 0 bit delay from framsync
             * MSB first
             * No extra bit padding
             * Padding bit (ignore)
             * slot Size is 24
             * Reads from DMA port
             * 0-bit rotation
             */
    
            /*I2S MODE*/
            /* .afsxctl  = */0x00000193, /* 3-slot  TDM mode,//0x4846 80AC
             * Frame sync is one word
             * internally generated frame sync
             * Falling edge is start of frame
             */
            /* .xtdm     = */0x00000007, /* 3 slots are active  */  // 0x4846 80B8
    
            /* .xintctl  = */0x000000b7, /* sync error,overrun error,clK error   */ //0x4846 80BC
            /* .xstat    = */0x000001FF, /* reset any existing status bits       */ //0x4846 80C0
            /* .xevtctl  = */0x00000000, /* DMA request is enabled or disabled   */ //0x4846 80CC
            
            { //25Mhz
    
                /* I2S MODE*/ // 0x4846 80B0  400Mhz/(3+1)/(3+1)=25Mhz
                /* .aclkxctl  = */0x00000023, /* Div (4), Internal Source, SYNC, Falling edge */
                /* .ahclkxctl = */0x00008003, /* Div (4), Internal AUX_CLK Source */
    
                /* .xclkchk   = */0x00ff0000 
            },
    
    };

    /* .aclkrctl = */0x000000a0,   //这里是不是要设置为0x000000a3  与发送时钟一致?测试后没有作用
    /* .ahclkrctl = */0x00008000  //这里是不是要设置为0x00008003 与发送时钟一致?

    我参考了这个帖子 https://e2e.ti.com/support/processors-group/processors/f/processors-forum/916088/am5728-mcasp-data-not-being-received?tisearch=e2e-sitesearch&keymatch=RCKFAIL#  ,但没有理解到TRM手册上的24.6.1的这几句话:

    The device have integrated eight McASP modules with:
    • McASP1 and McASP2 supporting up to 16 channels with independent TX/RX clock/sync domain
    • McASP3 through McASP8 modules supporting up to 4 channels with independent TX/RX clock/sync
    domain

    McASP module includes the following main features:
    • Two modules (McASP1 and McASP2) supporting up to 16 channels each and independent TX/RX
    clock/sync domains.
    • Six modules (McASP3, McASP4, McASP5, McASP6, McASP7, and McASP8) supporting up to 4
    channels each and unified clock/sync domain.

    这样描述是否有冲突,是独立的还是统一的时钟同步?我按照帖子的做法配置了不同步的方式,并配置了rx时钟寄存器分频与tx时钟寄存器分频一致,但是并没有找到如何配置MCASP3_ACLKR引脚和MCASP3_FSR引脚,因为我并没有找到这两个引脚,修改后的寄存器初始化配置如下:

    Mcasp_HwSetupData mcaspRcvSetup = {
            /* .rmask    = */0xFFFFFFFF,
            /* All the data bits are to be used     */
    
            /* .rfmt     = */0x000080b0,
            /* 0 bit delay from framsync
             * MSB first
             * No extra bit padding
             * Padding bit (ignore)
             * slot Size is 24
             * Reads from DMA port
             * NO rotation
             */
    
            /* .afsrctl  = */0x00000193, /* 3-slot TDM mode,
             * Frame sync is one word
             * Internally generated frame sync
             * Falling edge is start of frame
             */
    
            /* I2S MODE*/
            /* .rtdm     = */0x00000007, /* 3 slots are active
             *            */
    
            /* .rintctl  = */0x000000b3, /* sync error and overrun error         */
            /* .rstat    = */0x000001FF, /* reset any existing status bits       */
            /* .revtctl  = */0x00000000, /* DMA request is enabled or disabled   */
            
            { //25Mhz
    
                /* I2S MODE*/
                /* .aclkrctl  = */0x000000a3, /* Div (4), Internal Source, rising edge */
                /* .ahclkrctl = */0x00008003, /* Div (4), Internal AUX_CLK Source */
    
                /* .rclkchk   = */0x00ff0000 //0x4846 8088
            } 
    }; 
    
    Mcasp_HwSetupData mcaspXmtSetup = {
            /* .xmask    = */0xFFFFFFFF, /* All the data bits are to be used     */
            /* I2S MODE*/
            /* .xfmt     = */0x000080b0,  //0x4846 80A8
            /*
             * 0 bit delay from framsync
             * MSB first
             * No extra bit padding
             * Padding bit (ignore)
             * slot Size is 24
             * Reads from DMA port
             * 0-bit rotation
             */
    
            /*I2S MODE*/
            /* .afsxctl  = */0x00000193, /* 3-slot  TDM mode,//0x4846 80AC
             * Frame sync is one word
             * internally generated frame sync
             * Falling edge is start of frame
             */
            /* .xtdm     = */0x00000007, /* 3 slots are active  */  // 0x4846 80B8
    
            /* .xintctl  = */0x000000b7, /* sync error,overrun error,clK error   */ //0x4846 80BC
            /* .xstat    = */0x000001FF, /* reset any existing status bits       */ //0x4846 80C0
            /* .xevtctl  = */0x00000000, /* DMA request is enabled or disabled   */ //0x4846 80CC
            
            { //25Mhz
    
                /* I2S MODE*/ // 0x4846 80B0  400Mhz/(3+1)/(3+1)=25Mhz
                /* .aclkxctl  = */0x00000063, /* Div (4), Internal Source, ASYNC, Falling edge */
                /* .ahclkxctl = */0x00008003, /* Div (4), Internal AUX_CLK Source */
    
                /* .xclkchk   = */0x00ff0000 
            },
    
    };

    引脚以及时钟配置如下:

    void McASP3_Enable(void)
    {
    
        //uint32_t regVal = 0U;
    
        // Choose SYS_CLK2 (22.5792 MHZ) as source for ABE_PLL REF CLK
        HW_WR_FIELD32(
                CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG,
                CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG_CLKSEL,
                CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG_CLKSEL_SEL_SYS_CLK1);//0x4ae0 6118
    
        /* Reprogram ABE DPLL for 451.584 MHz output on PER_ABE_X1_GFCLK line */
    
        // step 1: disable the PLL, if enabled (ex: via GEL)
        while (HW_RD_FIELD32(
                CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG,
                CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN)
                == CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE)
            HW_WR_FIELD32(
                    CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG,
                    CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN,
                    CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_FR_BYP_MODE);
    
        // step 2: modify Synthesized Clock Parameters - DPLL MULT & DIV
        HW_WR_FIELD32(
                CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG,
                CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG_DPLL_MULT, 0xC8);//0x4a00 51ec  乘法 *200
    
        HW_WR_FIELD32(
                CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG,
                CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG_DPLL_DIV, 0x09);//分频  /10
    
        // step 3: Configure output clocks parameters - M2 = 1  M3 = 1
        HW_WR_FIELD32(
                CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_ABE_REG,
                CSL_CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_ABE_REG_DIVHS, 0x1);//0x4a00 51f0
        HW_WR_FIELD32(
                CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_ABE_REG,
                CSL_CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_ABE_REG_DIVHS, 0x1);//0x4a00 51f4
    
        // step 4: Confirm that the PLL has locked
        while (HW_RD_FIELD32(
                CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG,
                CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN)
                != CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE)
            HW_WR_FIELD32(
                    CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG,
                    CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN,
                    CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE);
    
        /* McASP3 Module Control */
        HW_WR_FIELD32(
                CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG,
                CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG_MODULEMODE,
                CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG_MODULEMODE_ENABLE);//0x4a00 9868  模块时钟显示启用
        while ((HW_RD_REG32(
                CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG)
                & CM_L4PER2_MCASP3_CLKCTRL_MODULEMODE_MASK) !=
        CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG_MODULEMODE_ENABLE)
            ;
    
        /* PAD IO Config for MCASP3 pins - ACLKX, AFSX, AXR0, AXR1*/
        HW_WR_FIELD32(
                CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_ACLKX,
                CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_ACLKX_MCASP3_ACLKX_MUXMODE,
                0); //0x4a00 3724
        HW_WR_FIELD32(
                CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_FSX,
                CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_FSX_MCASP3_FSX_MUXMODE,
                0); //0x4a00 3728
        HW_WR_FIELD32(
                CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR0,
                CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR0_MCASP3_AXR0_MUXMODE,
                0); //0x4a00 372c
        HW_WR_FIELD32(
                CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR1,
                CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR1_MCASP3_AXR1_MUXMODE,
                0); //0x4a00 3730
    
        //HW_WR_REG32(0x4AE06160, 0x1); // CM_CLKSEL_CLKOUT2: 0x1: Selects SYS_CLK2
        HW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG,
                      CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG_CLKSEL,
                      CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG_CLKSEL_SEL_SYS_CLK2); //0x4ae0 6160
    
        HW_WR_FIELD32(
                CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0,
                CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0_XREF_CLK0_INPUTENABLE, 0x0); // 0x0: Receive mode is disabled
    
        HW_WR_FIELD32(
                CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0,
                CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0_XREF_CLK0_MUXMODE, 0x9); //0x9: clkout2  //0x4a00 3694
    
        HW_WR_FIELD32(
                CSL_DSP_COREAON_CM_CORE_REGS+CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG,
                CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG_OPTFCLKEN_CLKOUTMUX2_CLK,
                CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG_OPTFCLKEN_CLKOUTMUX2_CLK_FCLK_EN); //0x4a00 86b0
    
    }

    期待您的解答,感谢!

  • 可否总结一下您目前需要咨询的问题,我帮您继续升级,谢谢!

  • 感谢回复!

    好的,目前MCASP能够实现时钟引脚、同步引脚、AXR发送引脚能够输出波形,但是不管是内部回环还是外部IO短接,始终收不到数据。

    问题1:缺少了什么配置?

    问题2:如何可以在不重新调用mcaspSubmitChan的情况下重新自动传输?也就是连续传输模式。

    谢谢!

  • 您好,我已经实现回环传输数据。

    因为我在不关闭通道的情况下时钟线会一直输出,而数据线和同步线只是在调用mcaspSubmitChan的时候才有波形,而我希望MCASP一直传输数据,在传输完成后自动更改缓冲区地址并重新传输(不再第二次调用mcaspSubmitChan函数)

    目前剩下的问题:MCASP如何自动连续传输数据?

    期待您的意见,感谢!

  • 您好,我更换了一种方式,已经实现了连续传输。

    部分程序如下:

    /*
     *  Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
     *
     *  Redistribution and use in source and binary forms, with or without
     *  modification, are permitted provided that the following conditions
     *  are met:
     *
     *    Redistributions of source code must retain the above copyright
     *    notice, this list of conditions and the following disclaimer.
     *
     *    Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the
     *    documentation and/or other materials provided with the
     *    distribution.
     *
     *    Neither the name of Texas Instruments Incorporated nor the names of
     *    its contributors may be used to endorse or promote products derived
     *    from this software without specific prior written permission.
     *
     *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
     *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
     *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
     *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     *
     */
     /**
     *  \file   mcaspTransmit.c
     *
     *  \brief  This file contains the McASP application, designed to meet specific
     *           requirements -
     *           1. Showcase bit clock of 10MHz
     *           2. Data output on two data lines
     *           3. The McASP to output the data on the lines and observe the same on the CRO.
     *
     */
    
    /* ========================================================================== */
    /*                             Include Files                                  */
    /* ========================================================================== */
    #include "stdint.h"
    #include "stdio.h"
    #include "string.h"
    #include <ti/csl/hw_types.h>
    #include <ti/csl/csl_mcasp.h>
    #include <ti/csl/csl_edma.h>
    #include <ti/csl/csl_i2c.h>
    #include <ti/csl/soc.h>
    #include <ti/sysbios/knl/Task.h>
    
    /* ========================================================================== */
    /*                           Macros & Typedefs                                */
    /* ========================================================================== */
    
    #if defined (SOC_AM574x) || defined (SOC_AM572x) || defined (SOC_TDA2XX) || defined (SOC_TDA2PX) || defined (SOC_DRA75x) || defined (SOC_AM571x) || defined (SOC_TDA2EX) || defined (SOC_DRA72x)
    #if defined (SOC_AM574x) || defined (SOC_AM572x) || defined (SOC_AM571x)
    #define SOC_MCASP_CFG_BASE CSL_MPU_MCASP1_CFG_REGS
    #define SOC_MCASP_BASE CSL_MPU_MCASP1_REGS
    #endif
    #if defined (SOC_TDA2XX) || defined (SOC_TDA2PX) || defined (SOC_TDA2EX) || defined (SOC_DRA72x) || defined (SOC_DRA75x)
    #define SOC_MCASP_CFG_BASE SOC_MCASP3_CFG_BASE
    #define SOC_MCASP_BASE SOC_MCASP3_BASE
    #endif
    #define SOC_MCASP_3_FIFO_REGS (SOC_MCASP_CFG_BASE + 0x1000)
    #define MCASP_RX_DMA_XBAR_INST            (128U)
    #define MCASP_TX_DMA_XBAR_INST            (129U)
    #else
    #define SOC_MCASP_CFG_BASE SOC_MCASP1_CFG_BASE
    #define SOC_MCASP_BASE SOC_MCASP1_BASE
    #define SOC_MCASP_1_FIFO_REGS (SOC_MCASP_CFG_BASE + 0x1000)
    #define MCASP_RX_DMA_XBAR_INST            (128U)
    #define MCASP_TX_DMA_XBAR_INST            (129U)
    #endif
    
    /*
    ** Values which are configurable
    */
    /* Slot size to send/receive data */
    #define SLOT_SIZE                         (32U)
    
    /* Word size to send/receive data. Word size <= Slot size */
    #define WORD_SIZE                         (32U)
    
    /* Number of channels, L & R */
    #define NUM_I2S_CHANNELS                  (2U)
    
    /* Number of samples to be used per audio buffer */
    #define NUM_SAMPLES_PER_AUDIO_BUF         (2000U)
    
    /* Number of buffers used per tx/rx */
    #define NUM_BUF                           (3U)
    
    /* Number of linked parameter set used per tx/rx */
    #define NUM_PAR                           (2U)
    
    /* Specify where the parameter set starting is */
    #define PAR_ID_START                      (72U)
    
    /* Number of samples in loop buffer */
    #define NUM_SAMPLES_LOOP_BUF              (10U)
    
    /* McASP Serializer 0 for Transmit */
    #define MCASP_XSER_TX_0                   (2U)
    
    /* McASP Serializer 1 for Transmit */
    #define MCASP_XSER_TX_1                   (3U)
    
    /*
    ** Below Macros are calculated based on the above inputs
    */
    
    #define I2S_SLOTS                         ((1 << NUM_I2S_CHANNELS) - 1)
    
    #define BYTES_PER_SAMPLE                  ((WORD_SIZE >> 3) \
                                               * NUM_I2S_CHANNELS)
    
    #define AUDIO_BUF_SIZE                    (NUM_SAMPLES_PER_AUDIO_BUF \
                                               * BYTES_PER_SAMPLE)
    
    #define TX_DMA_INT_ENABLE                 (EDMA3CC_OPT_TCC_SET            \
                                                   (EDMA3_CHA_MCASP_TX) | (1  \
                                                                           << \
                                                                           EDMA_TPCC_OPT_TCINTEN_SHIFT))
    
    #define PAR_TX_START                      (PAR_ID_START)
    
    /*
    ** Definitions which are not configurable
    */
    #define SIZE_PARAMSET                     (32U)
    #define OPT_FIFO_WIDTH                    (0x02 << 8U)
    
    /*
    ** Definitions which are configurable depending on the core to be used(ARM here)
    */
    #define EDMA3_CHA_MCASP_RX               (0)
    #define EDMA3_CHA_MCASP_TX               (1)
    
    #define EDMA3_CC_REGION_A15               (0U)
    #define EDMA3_CC_REGION_M4                (1U)
    
    #define EDMA3_CC_QUEUE                    (1U)
    
    #define EDMA3_CC_XFER_COMPLETION_INT_A15  (12U)
    #define EDMA3_CC_XFER_COMPLETION_INT_M4   (34U)
    
    #if defined (__ARM_ARCH_7A__)
    #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_A15
    #elif defined (__TI_ARM_V7M4__)
    #define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_M4
    #endif
    
    #define INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000U)
    #define INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010U)
    #define INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
    
    #define INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFU)
    #define INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
    #define INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
    
    #define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (230U)
    
    #define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)
    
    /*
    ** Definitions which are configurable depending on the application requirement
    */
    #define MCASP_ACLKX_CLKXDIV_VALUE         (0x2U)
    #define MCASP_AHCLKX_HCLKXDIV_VALUE       (0x5U)
    
    #define HSI2C_SLAVE_ADDR                  (0x26)
    
    #if defined (SOC_AM571x)
    #define SOC_I2Cx_BASE                  (CSL_MPU_I2C5_REGS)
    #elif defined (SOC_TDA2EX) || defined (SOC_DRA72x)
    #define SOC_I2Cx_BASE                  (SOC_I2C5_BASE)
    #elif defined (SOC_AM574x) || defined (SOC_AM572x)
    #define SOC_I2Cx_BASE                  (CSL_MPU_I2C2_REGS)
    #else
    #define SOC_I2Cx_BASE                  (SOC_I2C2_BASE)
    #endif
    
    /* ========================================================================== */
    /*                          Function prototypes                              */
    /* ========================================================================== */
    static void I2SDMAParamInit(void);
    static void McASPI2SConfigure(void);
    static void I2SDataTxActivate(void);
    void SetupI2C(uint8_t addr);
    void SetupI2CTransmit(void);
    void Configure_Edma_xbar();
    void padConfig_prcmEnable();
    void sampleConfigScr(unsigned int eventNum,
                        unsigned int chanNum);
    
    /* ========================================================================== */
    /*                            Global Variables                                */
    /* ========================================================================== */
    
    /* Global counters to keep track of errors. Can be removed before releasing  */
    uint32_t                       complInterruptCounter = 0x00;
    uint32_t                       errInterruptCounter   = 0x00;
    
    uint8_t                        dataToSlave;
    uint8_t                        dataFromSlave;
    
    /*
    ** Transmit buffers. If any new buffer is to be added, define it here and
    ** update the NUM_BUF.
    */
    static uint8_t                 txBuf0[AUDIO_BUF_SIZE];
    static uint8_t                 txBuf1[AUDIO_BUF_SIZE];
    static uint8_t                 txBuf2[AUDIO_BUF_SIZE];
    
    /*
    ** The offset of the paRAM ID sent, from starting of the paRAM set.
    */
    static volatile uint16_t       parOffSent = 0;
    
    typedef struct  {
        volatile unsigned int TPCC_EVTMUX[32];
    } IntmuxRegs;
    
    typedef volatile IntmuxRegs *IntmuxRegsOvly;
    
    /* Array of transmit buffer pointers */
    static uint32_t const          txBufPtr[NUM_BUF] =
    {
        (uint32_t) txBuf0,
        (uint32_t) txBuf1,
        (uint32_t) txBuf2
    };
    
    /*
    ** Default paRAM for Transmit section. This will be transmitting from
    ** a loop buffer.
    */
    static EDMA3CCPaRAMEntry const txDefaultPar =
    {
        (uint32_t) (OPT_FIFO_WIDTH),               /* Opt field */
        (uint32_t) txBuf0,                         /* source address */
        (uint16_t) (BYTES_PER_SAMPLE),             /* aCnt */
        (uint16_t) (NUM_SAMPLES_LOOP_BUF),         /* bCnt */
        (uint32_t) (SOC_MCASP_BASE),               /* dest address */
        (uint16_t) (BYTES_PER_SAMPLE),             /* source bIdx */
        (uint16_t) (0),                            /* dest bIdx */
        (uint16_t) (PAR_TX_START * SIZE_PARAMSET), /* link address */
        (uint16_t) (0),                            /* bCnt reload value */
        (uint16_t) (0),                            /* source cIdx */
        (uint16_t) (0),                            /* dest cIdx */
        (uint16_t) 1                               /* cCnt */
    };
    
    /* ========================================================================== */
    /*                          Function Definitions                              */
    /* ========================================================================== */
    void padConfig_prcmEnable()
    {
    #if defined (SOC_AM574x) || defined (SOC_AM572x) || defined (SOC_AM571x)
        /* Power on McASP instance 3 */
        HW_WR_REG32(0x4a009868, 0x02);
        while ((HW_RD_REG32(0x4a009868)) != 0x02U)
            {
                ;
            }
        /* Pad mux configuration for McASP instance 3 */
        HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_ACLKX,0xc0000);
        HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK2,0x40003);
        HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_FSX,0xc0000);
        HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR0,0xc0000);
        HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR1,0xc0000);
    #elif defined (SOC_TDA2XX) || defined (SOC_TDA2PX) || defined (SOC_TDA2EX) || defined (SOC_DRA72x) || defined (SOC_DRA75x)
         /* Power on McASP instance 3 */
        HW_WR_REG32(0x4a009868, 0x02);
        while ((HW_RD_REG32(0x4a009868)) != 0x02U)
            {
                ;
            }
        /* Pad mux configuration for McASP instance 3 */
        HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_MCASP3_ACLKX,0xc0000);
        HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_XREF_CLK2,0x40003);
        HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_MCASP3_FSX,0xc0000);
        HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_MCASP3_AXR0,0xc0000);
        HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_MCASP3_AXR1,0xc0000);
    #else
        /* Power on McASP instance 1 */
        HW_WR_REG32(SOC_IPU_CM_CORE_AON_BASE + CM_IPU_MCASP1_CLKCTRL, 0x02);
        while ((HW_RD_REG32(SOC_IPU_CM_CORE_AON_BASE + CM_IPU_MCASP1_CLKCTRL)) !=0x02U)
            {
                ;
            }
        /* Pad mux configuration for McASP instance 1 */
        HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_VOUT1_DE,0x00040001);
        HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_VOUT1_FLD,0x00040001);
        HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_VOUT1_D0,0x00040001);
        HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_VOUT1_D1,0x00040001);
    #endif
    
    #if defined (SOC_AM571x)
        /* Pad mux configuration for I2C instance 5 */
        HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP1_AXR0,0x5000A);
    #elif defined (SOC_TDA2EX) || defined (SOC_DRA72x)
        HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_MCASP1_AXR0,0x5000A);
    #elif defined (SOC_AM574x) || defined (SOC_AM572x)
        /* Pad mux configuration for I2C instance 2 */
        HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_I2C2_SDA,0x00);
    #elif defined (SOC_TDA2XX) || defined (SOC_TDA2PX) || defined (SOC_DRA75x)
        /* Pad mux configuration for I2C instance 2 */
        HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_I2C2_SDA,0x00);
    #elif defined (SOC_TDA3XX) || defined (SOC_DRA78x)
        /* Pad mux configuration for I2C instance 2 */
        HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_I2C2_SDA,0x00);
    #endif
    
    }
    
    void SetupI2C(uint8_t addr)
    {
        /* Put i2c in reset/disabled state */
        I2CMasterDisable(SOC_I2Cx_BASE);
    
        /* Configure i2c bus speed to 100khz */
        I2CMasterInitExpClk(SOC_I2Cx_BASE, 24000000,
                            8000000, 100000);
    
        I2CMasterEnableFreeRun(SOC_I2Cx_BASE);
    
        /* Set i2c slave address */
        I2CMasterSlaveAddrSet(SOC_I2Cx_BASE, addr);
    
        /* Bring i2c out of reset */
        I2CMasterEnable(SOC_I2Cx_BASE);
    }
    
    void SetupI2CTransmit(void)
    {
        /* Set data count */
        I2CSetDataCount(SOC_I2Cx_BASE, 2);
    
        /*
        ** Configure i2c as master-transmitter and to generate stop condition
        */
        I2CMasterControl(SOC_I2Cx_BASE, I2C_CFG_MST_TX);
    
        /*Enable transmit ready and stop condition interrupt*/
        I2CMasterIntEnableEx(SOC_I2Cx_BASE,
                             I2C_INT_TRANSMIT_READY | I2C_INT_STOP_CONDITION);
    
        /*Generate start conndition*/
        I2CMasterStart(SOC_I2Cx_BASE);
    
        /*Wait for transmit interrupt to occur*/
        while (I2CMasterIntStatusEx(SOC_I2Cx_BASE, I2C_INT_TRANSMIT_READY) != 0x10) ;
    
        /*Disable transmit ready and stop condition interrupt*/
        I2CMasterIntDisableEx(SOC_I2Cx_BASE, I2C_INT_TRANSMIT_READY);
    
        I2CMasterIntDisableEx(SOC_I2Cx_BASE, I2C_INT_STOP_CONDITION);
    
        /* Send first command word and then the data */
        I2CMasterDataPut(SOC_I2Cx_BASE, 0x00);
        I2CMasterDataPut(SOC_I2Cx_BASE, 0x00);
    }
    
    /*
    ** Initializes the DMA parameters.
    ** The TX basic paRAM set (channel) is 12.
    **
    ** The TX paRAM sets will be initialized to transmit from the loop buffer.
    ** The size of the loop buffer can be configured.
    ** The transfer completion interrupt will not be enabled for paRAM set 1;
    ** paRAM set 1 will be linked to linked paRAM set starting (PAR_TX_START) of TX.
    ** All other paRAM sets will be linked to itself.
    ** and further transmission only happens via linked paRAM set.
    ** For example, if the PAR_TX_START value is 72, and the number of paRAMS is 2,
    ** So transmission paRAM set linking will be initialized as 1-->72-->73, 73->73.
    */
    static void I2SDMAParamInit(void)
    {
        EDMA3CCPaRAMEntry paramSet;
        int i = 0;
    
        /* Initialize TX Buffers
         *
         * These patterns are seen/output on serializer0 and serializer1
         */
        for (i = 0; i < (AUDIO_BUF_SIZE / 4); i++)
        {
            if (0 == (i % 2))
            {
                int index;
                for (index = 0; index < 4; index++)
                {
                    /* '0xF0' data pattern that yields freq of 1.38MHz */
                    txBuf0[4 * i + index] = 0xF0U;
                    txBuf1[4 * i + index] = 0xF0U;
                    txBuf2[4 * i + index] = 0xF0U;
                }
            }
            else
            {
                int index;
                for (index = 0; index < 4; index++)
                {
                    /* '0xCC' data pattern that yields freq of 2.77MHz */
                    txBuf0[4 * i + index] = 0xCCU;
                    txBuf1[4 * i + index] = 0xCCU;
                    txBuf2[4 * i + index] = 0xCCU;
                }
            }
        }
    
        /* Initialize the 1st paRAM set for transmit */
        memcpy(&paramSet, &txDefaultPar, SIZE_PARAMSET - 2);
    
        EDMA3SetPaRAM(CSL_DSP_DSP_EDMA_CC_REGS, EDMA3_CHA_MCASP_TX, &paramSet);
    
        memcpy(&paramSet, &txDefaultPar, SIZE_PARAMSET - 2);
        /* Enable Intr for Link Channel */
        paramSet.opt     |= TX_DMA_INT_ENABLE;
        paramSet.srcAddr  = txBufPtr[1];
        paramSet.linkAddr = (PAR_TX_START * SIZE_PARAMSET);
        EDMA3SetPaRAM(CSL_DSP_DSP_EDMA_CC_REGS, (PAR_TX_START), &paramSet);
    
        memcpy(&paramSet, &txDefaultPar, SIZE_PARAMSET - 2);
        paramSet.srcAddr = txBufPtr[2];
        /* Self Link here */
        paramSet.linkAddr = ((PAR_TX_START + 1) * SIZE_PARAMSET);
    
        EDMA3SetPaRAM(CSL_DSP_DSP_EDMA_CC_REGS, (PAR_TX_START + 1), &paramSet);
    }
    
    /*
    ** Configures the McASP Transmit Section in I2S mode.
    */
    static void McASPI2SConfigure(void)
    {
        McASPTxReset(SOC_MCASP_CFG_BASE);
    
        /* Enable the FIFOs for DMA transfer */
        McASPWriteFifoEnable(SOC_MCASP_CFG_BASE, 2, 1);
    
        /* Set I2S format in the transmitter/receiver format units */
        McASPTxFmtI2SSet(SOC_MCASP_CFG_BASE, WORD_SIZE, SLOT_SIZE,
                         MCASP_TX_MODE_DMA);
    
        McASPTxFrameSyncCfg(SOC_MCASP_CFG_BASE, 2, MCASP_TX_FS_WIDTH_WORD,
                            MCASP_TX_FS_EXT_BEGIN_ON_FALL_EDGE |
                            MCASP_TX_FS_INTERNAL);
    
        /* configure the clock for transmitter */
        McASPTxClkCfg(SOC_MCASP_CFG_BASE, MCASP_TX_CLK_INTERNAL,
                      ((MCASP_ACLKX_CLKXDIV_VALUE &
                        MCASP_ACLKXCTL_CLKXDIV_MASK) >>
                       MCASP_ACLKXCTL_CLKXDIV_SHIFT),
                      ((MCASP_AHCLKX_HCLKXDIV_VALUE &
                        MCASP_AHCLKXCTL_HCLKXDIV_MASK) >>
                       MCASP_AHCLKXCTL_HCLKXDIV_SHIFT));
    
        McASPTxClkPolaritySet(SOC_MCASP_CFG_BASE, MCASP_TX_CLK_POL_FALL_EDGE);
    
        McASPTxClkCheckConfig(SOC_MCASP_CFG_BASE, MCASP_TX_CLKCHCK_DIV32,
                              0x00, 0xFF);
    
        /* Enable the transmitter/receiver slots. I2S uses 2 slots */
        McASPTxTimeSlotSet(SOC_MCASP_CFG_BASE, I2S_SLOTS);
    
        /*
        ** Set the serializers
        */
        McASPSerializerTxSet(SOC_MCASP_CFG_BASE, MCASP_XSER_TX_0);
        McASPSerializerTxSet(SOC_MCASP_CFG_BASE, MCASP_XSER_TX_1);
    
        /*
        ** Configure the McASP pins
        ** Output - Frame Sync, Clock, Serializer Rx and Serializer Tx
        **          (Clocks generated internally)
        */
        McASPPinMcASPSet(SOC_MCASP_CFG_BASE, (MCASP_PIN_AFSR |
                                              MCASP_PIN_ACLKR | MCASP_PIN_AFSX |
                                              MCASP_PIN_AHCLKX |
                                              MCASP_PIN_ACLKX |
                                              MCASP_PIN_AMUTE |
                                              MCASP_PIN_AXR(MCASP_XSER_TX_0) |
                                              MCASP_PIN_AXR(MCASP_XSER_TX_1)));
    
        McASPPinDirOutputSet(SOC_MCASP_CFG_BASE, MCASP_PIN_AFSR);
        McASPPinDirOutputSet(SOC_MCASP_CFG_BASE, MCASP_PIN_ACLKR);
    
        McASPPinDirOutputSet(SOC_MCASP_CFG_BASE, MCASP_PIN_AFSX);
    
        /* Configure high clock as Output */
        McASPPinDirOutputSet(SOC_MCASP_CFG_BASE, MCASP_PIN_AHCLKX);
    
        McASPPinDirOutputSet(SOC_MCASP_CFG_BASE, MCASP_PIN_ACLKX);
    
        /* Both Serializers used to output data out */
        McASPPinDirOutputSet(SOC_MCASP_CFG_BASE, MCASP_PIN_AXR(MCASP_XSER_TX_0));
        McASPPinDirOutputSet(SOC_MCASP_CFG_BASE, MCASP_PIN_AXR(MCASP_XSER_TX_1));
    }
    
    /*
    ** Activates the data transmission/reception
    ** The DMA parameters shall be ready before calling this function.
    */
    static void I2SDataTxActivate(void)
    {
        /* Start the clocks */
        McASPTxClkStart(SOC_MCASP_CFG_BASE, MCASP_TX_CLK_INTERNAL);
    
        /* Enable EDMA for the transfer */
        EDMA3EnableTransfer(CSL_DSP_DSP_EDMA_CC_REGS, EDMA3_CHA_MCASP_TX,
                            EDMA3_TRIG_MODE_EVENT);
    
        /* Activate the  serializers */
        McASPTxSerActivate(SOC_MCASP_CFG_BASE);
    
        /* make sure that the XDATA bit is cleared to zero */
        while (McASPTxStatusGet(SOC_MCASP_CFG_BASE) & MCASP_TX_STAT_DATAREADY) ;
    
        /* Activate the state machines */
        McASPTxEnable(SOC_MCASP_CFG_BASE);
    }
    
    void sampleConfigScr1(unsigned int eventNum,
                         unsigned int chanNum)
    {
        unsigned int   scrChanOffset = 0;
        unsigned int   scrRegOffset  = 0;
        unsigned int   xBarEvtNum    = 0;
        IntmuxRegsOvly scrEvtMux     =
            (IntmuxRegsOvly) (EDMA3_EVENT_MUX_REG_BASE_ADDR);
    
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
            (chanNum < EDMA3_NUM_TCC))
        {
            scrRegOffset  = chanNum / 2;
            scrChanOffset = chanNum - (scrRegOffset * 2);
            xBarEvtNum    = (eventNum + 1);
    
            switch (scrChanOffset)
            {
                case 0:
                    scrEvtMux->TPCC_EVTMUX[scrRegOffset] &=
                        ~(INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
                    scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                        (xBarEvtNum & INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
                    break;
                case 1:
                    scrEvtMux->TPCC_EVTMUX[scrRegOffset] &=
                        ~(INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK);
                    scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                        ((xBarEvtNum <<
                          INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
                         (INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
                    break;
                default:
                    break;
            }
        }
    }
    
    void Configure_Edma_xbar()
    {
        sampleConfigScr1(MCASP_RX_DMA_XBAR_INST, EDMA3_CHA_MCASP_TX);
    }
    
    /*
    ** The main function. Application starts here.
    */
    int mcasp_test_Task(void)
    {
        uint32_t loopHere = 1;
    
        /*pad config and prcm enable*/
    //    padConfig_prcmEnable();
    
    //    SetupI2C(HSI2C_SLAVE_ADDR);
    
        /*Clear 6th bit i.e VIN6_SEL_S0 line*/
    //    SetupI2CTransmit();
    
    #if defined (__ARM_ARCH_7A__)
        EDMAsetRegion(EDMA3_CC_REGION_A15);
    #elif defined (__TI_ARM_V7M4__)
        EDMAsetRegion(EDMA3_CC_REGION_M4);
    #endif
    
        EDMA3Init(CSL_DSP_DSP_EDMA_CC_REGS, EDMA3_CC_QUEUE);
    
        Configure_Edma_xbar();
    
        /* Request EDMA channels */
        EDMA3RequestChannel(CSL_DSP_DSP_EDMA_CC_REGS,
                            EDMA3_CHANNEL_TYPE_DMA,
                            EDMA3_CHA_MCASP_TX,
                            EDMA3_CHA_MCASP_TX,
                            EDMA3_CC_QUEUE);
    
        /* Initialize the DMA parameters */
        I2SDMAParamInit();
    
        /* Configure the McASP for I2S */
        McASPI2SConfigure();
    
        /* Activate the audio transmission and reception */
        I2SDataTxActivate();
    
        /*
        ** Loop forever.
        */
        uint8_t j = 0;
        while (loopHere)
            {
    
            memset(txBuf0,j++,AUDIO_BUF_SIZE);
    //        memset(txBuf1,j++,AUDIO_BUF_SIZE);
            memset(txBuf2,j++,AUDIO_BUF_SIZE);
    
            EDMA3CCPaRAMEntry paramSet;
                int i = 0;
    
                /* Initialize the 1st paRAM set for transmit */
                memcpy(&paramSet, &txDefaultPar, SIZE_PARAMSET - 2);
    
                EDMA3SetPaRAM(CSL_DSP_DSP_EDMA_CC_REGS, EDMA3_CHA_MCASP_TX, &paramSet);
    
                memcpy(&paramSet, &txDefaultPar, SIZE_PARAMSET - 2);
                /* Enable Intr for Link Channel */
                paramSet.opt     |= TX_DMA_INT_ENABLE;
                paramSet.srcAddr  = txBufPtr[1];
                paramSet.linkAddr = (PAR_TX_START * SIZE_PARAMSET);
                EDMA3SetPaRAM(CSL_DSP_DSP_EDMA_CC_REGS, (PAR_TX_START), &paramSet);
    
                memcpy(&paramSet, &txDefaultPar, SIZE_PARAMSET - 2);
                paramSet.srcAddr = txBufPtr[2];
                /* Self Link here */
                paramSet.linkAddr = ((PAR_TX_START + 1) * SIZE_PARAMSET);
    
                EDMA3SetPaRAM(CSL_DSP_DSP_EDMA_CC_REGS, (PAR_TX_START + 1), &paramSet);
                Task_sleep(1);
            }
    
        return 0;
    }
    /***************************** End Of File ***********************************/
    

    感谢您的帮助!