TI的工程师您好，我在使用AM5718的DSP核测试MCASP回环程序时遇到了一个问题，时钟线能输出我设置的频率对应的波形，同步线也一样，但是AXR引脚无法输出波形，接收缓冲区也无法接收到数据，设置的回调函数也无法触发，我在传输后查看TXSTAT和RXSTAT寄存器的值分别是0x171和0x175，也就是传输出现了错误，我在论坛上看了很多帖子，同时也查看了很多手册，没有找到哪里出了问题，希望您能帮我解答疑惑。
部分测试程序如下：
/*
* bsp_mcasp.c
*
* Created on: 2022年3月10日
* Author: lhy0611
*/
/* XDCtools Header files */
#include <xdc/std.h>
#include <xdc/cfg/global.h>
#include <xdc/runtime/System.h>
#include <xdc/runtime/Error.h>
#include <xdc/runtime/Diags.h>
#include <xdc/runtime/Log.h>
#include <xdc/runtime/Assert.h>
#include <xdc/runtime/Registry.h>
#include <xdc/runtime/IHeap.h>
#include <xdc/runtime/Memory.h>
/* BIOS Header files */
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Clock.h>
#include <ti/sysbios/heaps/HeapMem.h>
#include <ti/sysbios/hal/Hwi.h>
#include <ti/sysbios/knl/Swi.h>
#include <ti/ipc/Ipc.h>
#include <ti/ipc/MessageQ.h>
#include <ti/ipc/MultiProc.h>
#include <ti/sysbios/knl/Semaphore.h>
#include <stdio.h>
#include <ti/csl/example/utils/common/inc/app_utils.h>
#include <ti/csl/soc.h>
#include <ti/csl/hw_types.h>
#include <ti/csl/csl_edma.h>
#include <ti/csl/csl_chip.h>
#include <ti/csl/arch/csl_arch.h>
/* TI-RTOS Header files */
#include <ti/drv/gpio/GPIO.h>
#include <ti/drv/gpio/soc/GPIO_soc.h>
#include <ti/drv/gpio/test/led_blink/src/GPIO_log.h>
#include <ti/drv/gpio/test/led_blink/src/GPIO_board.h>
#include <ti/board/board.h>
#include <ti/osal/osal.h>
#include <ti/osal/CacheP.h>
/* EDMA3 头文件 */
#include <ti/sdo/edma3/drv/edma3_drv.h>
#include <ti/sdo/edma3/rm/edma3_rm.h>
#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
#include <ti/drv/mcasp/mcasp_drv.h>
#include <ti/drv/mcasp/mcasp_osal.h>
#include <ti/drv/mcasp/soc/mcasp_soc.h>
#include <ti/csl/csl_mcasp.h>
#include <bsp_mcasp.h>
#include <mcasp_cfg.h>
#include <mcasp_drv.h>
#include <mcasp_tune.h>
void Configure_XBAR(void)
{
/* Mapping the DMA crossbar for McASP DMA_DREQ_(128-120) in to EDMA3_DREQ_0-15.
* The EDMA3_DREQ_0-15 correspond to (CSL_EDMA3_CHA_MCASP'n'_RX) which are
* used inside mcasp_soc.c to register EDMA. Please note that the API below takes
* the mapped DMAReq with 1 as the base, whereas CSL_EDMA3_CHA_MCASP'n'
* are with base 0 */
CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 128,
1 + CSL_EDMA3_CHA_MCASP0_RX);
CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 129,
1 + CSL_EDMA3_CHA_MCASP0_TX);
CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 130,
1 + CSL_EDMA3_CHA_MCASP1_RX);
CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 131,
1 + CSL_EDMA3_CHA_MCASP1_TX);
CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 132,
1 + CSL_EDMA3_CHA_MCASP2_RX);
CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 133,
1 + CSL_EDMA3_CHA_MCASP2_TX);
CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 134,
1 + CSL_EDMA3_CHA_MCASP3_RX);
CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 135,
1 + CSL_EDMA3_CHA_MCASP3_TX);
CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 136,
1 + CSL_EDMA3_CHA_MCASP4_RX);
CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 137,
1 + CSL_EDMA3_CHA_MCASP4_TX);
CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 138,
1 + CSL_EDMA3_CHA_MCASP5_RX);
CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 139,
1 + CSL_EDMA3_CHA_MCASP5_TX);
CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 140,
1 + CSL_EDMA3_CHA_MCASP6_RX);
CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 141,
1 + CSL_EDMA3_CHA_MCASP6_TX);
CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 142,
1 + CSL_EDMA3_CHA_MCASP7_RX);
CSL_xbarDmaConfigure(CSL_XBAR_DMA_CPU_ID_EDMA, 143,
1 + CSL_EDMA3_CHA_MCASP7_RX);
}
void configMcASP_SocHwInfo(void)
{
/* Configure the interrupts for the McASP Instance MCASP_NUM */
/* ON Keystone, it involves CIC programming as well.
* The McASP does that internally, if configured with the correct parameters.
* Such as muxNum, muxInEvent, muxOutEvent,
* cpuInEventNum, cpuIntNum
*/
Mcasp_HwInfo hwInfo;
Mcasp_socGetInitCfg(MCASP_NUM, &hwInfo);
if ((hwInfo.rxMuxOutEvent == MCASP_UNASSIGNED_MUX_EVENTNUM)
|| (hwInfo.txMuxOutEvent == MCASP_UNASSIGNED_MUX_EVENTNUM))
{
#ifdef _TMS320C6X
/* Choosing a free Crossbar Instance number from Table 17-3. DSP1_INTC Default Interrupt Mapping
* in the AM572x TRM . Please note that this is fore Core 0 , i.e DSP1 only*/
/* Freely available cross bar instance numbers for DSP1 */
hwInfo.txMuxOutEvent = CSL_XBAR_INST_DSP1_IRQ_74;
hwInfo.rxMuxOutEvent = CSL_XBAR_INST_DSP1_IRQ_75;
/* The CPU event numbers corresponding to the above */
hwInfo.cpuTxEventNumber = 74;
hwInfo.cpuRxEventNumber = 75;
#endif
}
/* Write back */
Mcasp_socSetInitCfg(MCASP_NUM, &hwInfo);
}
extern EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[];
static void enableEDMAHwEvent(uint32_t edmaNum, uint32_t eventNo)
{
sampleEdma3GblCfgParams[edmaNum].dmaChannelHwEvtMap[eventNo / 32] |= (1
<< (eventNo % 32));
}
EDMA3_DRV_Handle McaspApp_edmaInit(Mcasp_HwInfo *cfg)
{
EDMA3_DRV_Handle hEdma;
EDMA3_DRV_Result edmaResult = 0;
enableEDMAHwEvent(EDMACC_NUM, CSL_EDMA3_CHA_MCASP2_RX);
enableEDMAHwEvent(EDMACC_NUM, CSL_EDMA3_CHA_MCASP2_TX);
hEdma = edma3init(EDMACC_NUM, &edmaResult);
if (edmaResult != EDMA3_DRV_SOK)
{
/* Report EDMA Error
*/
System_printf("\nEDMA driver initialization unsuccessful\n");
}
else
{
System_printf("\nEDMA driver initialization successful.\n");
}
return hEdma;
}
void mcaspAppCallback(void *arg, MCASP_Packet *ioBuf)
{
System_printf("\nmcaspAppCallback.\n");
if (ioBuf->cmd == MCASP_READ)
{
}
else if (ioBuf->cmd == MCASP_WRITE)
{
}
else
{
}
}
Mcasp_HwSetupData mcaspRcvSetup = {
/* .rmask = */0xFFFFFFFF,
/* All the data bits are to be used */
/* .rfmt = */0x000080b0,
/* 0 bit delay from framsync
* MSB first
* No extra bit padding
* Padding bit (ignore)
* slot Size is 24
* Reads from DMA port
* NO rotation
*/
/* .afsrctl = */0x00000193, /* 3-slot TDM mode,
* Frame sync is one word
* Internally generated frame sync
* Falling edge is start of frame
*/
/* I2S MODE*/
/* .rtdm = */0x00000007, /* 3 slots are active
* */
/* .rintctl = */0x000000b3, /* sync error and overrun error */
/* .rstat = */0x000001FF, /* reset any existing status bits */
/* .revtctl = */0x00000000, /* DMA request is enabled or disabled */
{ //25Mhz
/* I2S MODE*/
/* .aclkrctl = */0x00000023, /* Div (4), Internal Source, rising edge */
/* .ahclkrctl = */0x00008003, /* Div (4), Internal AUX_CLK Source */
/* .rclkchk = */0x00000000 } };
Mcasp_HwSetupData mcaspXmtSetup = {
/* .xmask = */0xFFFFFFFF, /* All the data bits are to be used */
/* I2S MODE*/
/* .xfmt = */0x000080b0, //0x4846 80A8
/*
* 0 bit delay from framsync
* MSB first
* No extra bit padding
* Padding bit (ignore)
* slot Size is 24
* Reads from DMA port
* 0-bit rotation
*/
/*I2S MODE*/
/* .afsxctl = */0x00000193, /* 3-slot TDM mode,//0x4846 80AC
* Frame sync is one word
* internally generated frame sync
* Falling edge is start of frame
*/
/* .xtdm = */0x00000007, /* 3 slots are active */ // 0x4846 80B8
/* .xintctl = */0x000000b7, /* sync error,overrun error,clK error */ //0x4846 80BC
/* .xstat = */0x000001FF, /* reset any existing status bits */ //0x4846 80C0
/* .xevtctl = */0x00000000, /* DMA request is enabled or disabled */ //0x4846 80CC
{ //25Mhz
/* I2S MODE*/ // 0x4846 80B0
/* .aclkxctl = */0x00000023, /* Div (4), Internal Source, SYNC, Falling edge */
/* .ahclkxctl = */0x00008003, /* Div (4), Internal AUX_CLK Source */
/* .xclkchk = */0x00000000 },
};
/* The below variables are used to quit the frame processing loop if an error occurs */
int gblErrFlagXmt = 0;
int gblErrFlagRcv = 0;
/* The below variables are used to analyze the errors if an error interrupt happens */
Mcasp_errCbStatus errCbStatusXmt;
Mcasp_errCbStatus errCbStatusRcv;
/* Error handler for Transmit side */
void GblErrXmt(Mcasp_errCbStatus errCbStat)
{
gblErrFlagXmt = 1;
errCbStatusXmt = errCbStat;
System_printf("GblErrXmt\n");
}
/* Error handler for Rcv side */
void GblErrRcv(Mcasp_errCbStatus errCbStat)
{
gblErrFlagRcv = 1;
errCbStatusRcv = errCbStat;
System_printf("GblErrRcv\n");
}
Mcasp_Params mcaspParams;
Ptr hMcaspDev;
/* McAsp channel parameters */
Mcasp_ChanParams mcasp_txchanparam = { //
.noOfSerRequested = TX_NUM_SERIALIZER, //1
.indexOfSersRequested = { Mcasp_SerializerNum_0 }, //
.mcaspSetup = &mcaspXmtSetup, //
.isDmaDriven = TRUE, .channelMode = Mcasp_OpMode_TDM, //
.wordWidth = Mcasp_WordLength_24, //
.userLoopJobBuffer = NULL, .userLoopJobLength = 0, //
.edmaHandle = NULL, //
.gblCbk = (Mcasp_GblCallback) &GblErrXmt, //
.noOfChannels = 1, //
.dataFormat = Mcasp_BufferFormat_1SER_MULTISLOT_NON_INTERLEAVED, //
.enableHwFifo = TRUE, //
.hwFifoEventDMARatio = TX_FIFO_EVENT_DMA_RATIO, //
.isDataPacked = TRUE, //
.wordBitsSelect = Mcasp_WordBitsSelect_LSB //
};
Mcasp_ChanParams mcasp_rxchanparam = { //
.noOfSerRequested = RX_NUM_SERIALIZER, //1
.indexOfSersRequested = { Mcasp_SerializerNum_1 }, //
.mcaspSetup = &mcaspRcvSetup, //
.isDmaDriven = TRUE, //
.channelMode = Mcasp_OpMode_TDM, //
.wordWidth = Mcasp_WordLength_24, //
.userLoopJobBuffer = NULL, //
.userLoopJobLength = 0, //
.edmaHandle = NULL, //
.gblCbk = (Mcasp_GblCallback) &GblErrRcv, //
.noOfChannels = 1, //
.dataFormat = Mcasp_BufferFormat_1SER_MULTISLOT_NON_INTERLEAVED, //
.enableHwFifo = TRUE, //
.hwFifoEventDMARatio = RX_FIFO_EVENT_DMA_RATIO, //
.isDataPacked = TRUE, //
.wordBitsSelect = Mcasp_WordBitsSelect_LSB //
};
/* Channel Handles */
Ptr hMcaspTxChan;
Ptr hMcaspRxChan;
/**************************************************************************************/
/* FUNCTION DESCRIPTION: This utility function converts local GEM L2 address in to global
memory addresses used by the EDMA inside McASP
*/
/**************************************************************************************/
static uintptr_t getGlobalAddr(uintptr_t addr)
{
if ((addr >= 0x800000) && (addr < 0x1000000))
{
#ifdef _TMS320C6X
uint32_t coreNum;
/* Get the core number. */
coreNum = CSL_chipReadReg(CSL_CHIP_DNUM);
#if defined(SOC_AM572x) || defined(SOC_AM571x)
/* Compute the global address. */
return ((1 << 30) | (coreNum << 24) | (addr & 0x00ffffff));
#else
/* Compute the global address. */
return ((1 << 28) | (coreNum << 24) | (addr & 0x00ffffff));
#endif
#else
return addr;
#endif
}
else
{
/* non-L2 address range */
return addr;
}
}
/*
* ======== prime ========
*/
MCASP_Packet rxFrame;
MCASP_Packet txFrame;
#pragma DATA_SECTION (rxbuf,".l2sram")
#pragma DATA_ALIGN (rxbuf,128)
uint8_t rxbuf[100];
#pragma DATA_SECTION (txbuf,".l2sram")
#pragma DATA_ALIGN (txbuf,128)
uint8_t txbuf[100];
Void mcasp_test_Task(void)
{
Mcasp_HwInfo hwInfo;
volatile int32_t i32Count, status = 0;
int32_t count = 0;
Mcasp_socGetInitCfg(MCASP_NUM, &hwInfo);
hwInfo.dmaHandle = McaspApp_edmaInit(&hwInfo);
Mcasp_socSetInitCfg(MCASP_NUM, &hwInfo);
mcaspParams = Mcasp_PARAMS;
mcaspParams.mcaspHwSetup.glb.dlbMode = (CSL_MCASP_DLBCTL_DLBEN_ENABLE
| ( CSL_MCASP_DLBCTL_ORD_XMTEVEN << CSL_MCASP_DLBCTL_ORD_SHIFT)
| ( CSL_MCASP_DLBCTL_MODE_XMTCLK << CSL_MCASP_DLBCTL_MODE_SHIFT));
status = mcaspBindDev(&hMcaspDev, MCASP_NUM, &mcaspParams);
if ((status != MCASP_COMPLETED) || (hMcaspDev == NULL))
{
System_printf("mcaspBindDev for McASP Failed\n");
// abort();
}
else
{
System_printf("mcaspBindDev for McASP success\n");
}
/* Create Mcasp channel for Tx */
status = mcaspCreateChan(&hMcaspTxChan, hMcaspDev, MCASP_OUTPUT,
&mcasp_txchanparam, mcaspAppCallback, NULL);
if ((status != MCASP_COMPLETED) || (hMcaspTxChan == NULL))
{
System_printf("mcaspCreateChan for McASP3 Tx Failed %d\n", status);
// BIOS_exit(0);
}
else
{
System_printf("mcaspCreateChan for McASP3 Tx success\n");
}
/* Create Mcasp channel for Rx */
status = mcaspCreateChan(&hMcaspRxChan, hMcaspDev, MCASP_INPUT,
&mcasp_rxchanparam, mcaspAppCallback, NULL);
if ((status != MCASP_COMPLETED) || (hMcaspRxChan == NULL))
{
System_printf("mcaspCreateChan for McASP3 Rx Failed\n");
// BIOS_exit(0);
}
else
{
System_printf("mcaspCreateChan for McASP3 Rx success\n");
}
uint32_t tx_bytes_per_sample = (mcasp_txchanparam.wordWidth / 8);
uint32_t rx_bytes_per_sample = (mcasp_rxchanparam.wordWidth / 8);
uint32_t tx_frame_size = mcasp_txchanparam.noOfSerRequested
* tx_bytes_per_sample;
uint32_t rx_frame_size = mcasp_rxchanparam.noOfSerRequested
* rx_bytes_per_sample;
System_printf("rx_frame_size:%d,tx_frame_size:%d\n", rx_frame_size,
tx_frame_size);
// rxbuf = malloc(rx_frame_size);
// txbuf = malloc(tx_frame_size);
memset(rxbuf, 0, rx_frame_size);
memset(txbuf, 3, tx_frame_size);
rxFrame.cmd = MCASP_READ;
rxFrame.addr = rxbuf; //(void*)(getGlobalAddr((uintptr_t) rxbuf));
rxFrame.size = rx_frame_size;
rxFrame.arg = (uintptr_t) hMcaspRxChan;
rxFrame.status = 0;
rxFrame.misc = 1; /* reserved - used in callback to indicate asynch packet */
status = mcaspSubmitChan(hMcaspRxChan, &rxFrame);
if ((status != MCASP_PENDING))
{
System_printf(
"Debug: Error McASP3 RX : Prime buffer #%d submission FAILED\n",
status);
}
else
{
System_printf(
"Debug: McASP3 RX : Prime buffer #%d submission Success\n",
status);
}
txFrame.cmd = MCASP_WRITE;
txFrame.addr = txbuf; //(void*) (getGlobalAddr((uintptr_t) txbuf));
txFrame.size = tx_frame_size;
txFrame.arg = (uintptr_t) hMcaspTxChan;
txFrame.status = 0;
txFrame.misc = 1; /* reserved - used in callback to indicate asynch packet */
status = mcaspSubmitChan(hMcaspTxChan, &txFrame);
if ((status != MCASP_PENDING))
{
System_printf(
"Debug: Error McASP3 TX : Prime buffer #%d submission FAILED\n",
status);
}
else
{
System_printf(
"Debug: McASP3 TX : Prime buffer #%d submission Success\n",
status);
}
Task_sleep(1000);
int cnt = 0;
for (cnt = 0; cnt < tx_frame_size; cnt++)
{
System_printf("txbuf[%d]:%d,rxbuf[%d]:%d\r\n", cnt, txbuf[cnt], cnt,
rxbuf[cnt]);
}
status = McASPTxStatusGet(CSL_MPU_MCASP3_CFG_REGS); //0x4846 80c0
System_printf("Txstatus:%x\r\n", status);
status = McASPRxStatusGet(CSL_MPU_MCASP3_CFG_REGS); //0x4846 8080
System_printf("Rxstatus:%x\r\n", status);
//
// status = mcaspControlChan(hMcaspRxChan, Mcasp_IOCTL_CHAN_PARAMS_WORD_WIDTH,
// &mcasp_chanparam[0]);
status = mcaspDeleteChan(hMcaspRxChan);
System_printf("Deleting Rx channel %d\r\n", status);
status = mcaspDeleteChan(hMcaspTxChan);
System_printf("Deleting Tx channel %d\r\n", status);
status = mcaspUnBindDev(hMcaspDev);
System_printf("UnBinding Mcasp %d\r\n", status);
}
void McASP3_Enable(void)
{
//uint32_t regVal = 0U;
// Choose SYS_CLK2 (22.5792 MHZ) as source for ABE_PLL REF CLK
HW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG, \
CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG_CLKSEL, \
CSL_CKGEN_PRM_CM_CLKSEL_ABE_PLL_SYS_REG_CLKSEL_SEL_SYS_CLK1);
/* Reprogram ABE DPLL for 451.584 MHz output on PER_ABE_X1_GFCLK line */
// step 1: disable the PLL, if enabled (ex: via GEL)
while(HW_RD_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG, \
CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN) == CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE)
HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG, \
CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN, \
CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_FR_BYP_MODE);
// step 2: modify Synthesized Clock Parameters - DPLL MULT & DIV
HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG, \
CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG_DPLL_MULT, \
0xC8);
HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG, \
CSL_CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG_DPLL_DIV, \
0x09);
// step 3: Configure output clocks parameters - M2 = 1 M3 = 1
HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_ABE_REG, \
CSL_CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_ABE_REG_DIVHS, \
0x1);
HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_ABE_REG, \
CSL_CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_ABE_REG_DIVHS, \
0x1);
// step 4: Confirm that the PLL has locked
while(HW_RD_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG, \
CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN) != CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE)
HW_WR_FIELD32(CSL_DSP_CKGEN_CM_CORE_AON_REGS+CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG, \
CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN, \
CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE);
/* McASP3 Module Control */
HW_WR_FIELD32(CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG, \
CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG_MODULEMODE, \
CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG_MODULEMODE_ENABLE);
while ((HW_RD_REG32(CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG) & CM_L4PER2_MCASP3_CLKCTRL_MODULEMODE_MASK) != \
CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG_MODULEMODE_ENABLE) ;
/* PAD IO Config for McASP3 pins - ACLKX, AFSX, AXR0, AXR1*/
HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_ACLKX, \
CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_ACLKX_MCASP3_ACLKX_MUXMODE, \
0xc0000);//0x4a00 3724
HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_FSX, \
CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_FSX_MCASP3_FSX_MUXMODE, \
0xc0000);//0x4a00 3728
HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR0, \
CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR0_MCASP3_AXR0_MUXMODE, \
0xc0000);//0x4a00 372c
HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR1, \
CSL_CONTROL_CORE_PAD_IO_PAD_MCASP3_AXR1_MCASP3_AXR1_MUXMODE, \
0xc0000);//0x4a00 3730
//HW_WR_REG32(0x4AE06160, 0x1); // CM_CLKSEL_CLKOUT2: 0x1: Selects SYS_CLK2
HW_WR_FIELD32(CSL_DSP_CKGEN_PRM_REGS+CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG, \
CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG_CLKSEL, \
CSL_CKGEN_PRM_CM_CLKSEL_CLKOUTMUX2_REG_CLKSEL_SEL_SYS_CLK2);//0x4ae0 6160
HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0, \
CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0_XREF_CLK0_INPUTENABLE, \
0x0); // 0x0: Receive mode is disabled
HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0, \
CSL_CONTROL_CORE_PAD_IO_PAD_XREF_CLK0_XREF_CLK0_MUXMODE, \
0x9); //0x9: clkout2 //0x4a00 3694
HW_WR_FIELD32(CSL_DSP_COREAON_CM_CORE_REGS+CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG, \
CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG_OPTFCLKEN_CLKOUTMUX2_CLK, \
CSL_COREAON_CM_CORE_CM_COREAON_DUMMY_MODULE2_CLKCTRL_REG_OPTFCLKEN_CLKOUTMUX2_CLK_FCLK_EN);//0x4a00 86b0
}
/***************************** End Of File ***********************************/
期待您的回复，感谢！
