AM5718: DSP核使用MCASP EDMA无法连续接收数据

/*
 *  Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
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 *    from this software without specific prior written permission.
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/**
 *  \file   mcaspTransmit.c
 *
 *  \brief  This file contains the McASP application, designed to meet specific
 *           requirements -
 *           1. Showcase bit clock of 10MHz
 *           2. Data output on two data lines
 *           3. The McASP to output the data on the lines and observe the same on the CRO.
 *
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
#include "stdint.h"
#include "stdio.h"
#include "string.h"
#include <ti/csl/hw_types.h>
#include <ti/csl/csl_mcasp.h>
#include <ti/csl/csl_edma.h>
#include <ti/csl/soc.h>
#include <ti/sysbios/knl/Task.h>
#include <xdc/runtime/System.h>
#include <ti/csl/arch/c67x/interrupt.h>
#include <ti/sysbios/hal/Hwi.h>

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */

#define SOC_MCASP_CFG_BASE CSL_MPU_MCASP1_CFG_REGS
#define SOC_MCASP_BASE CSL_MPU_MCASP1_REGS

#define MCASP_RX_DMA_XBAR_INST            (128U)
#define MCASP_TX_DMA_XBAR_INST            (129U)

/*
 ** Values which are configurable
 */
/* Slot size to send/receive data */
#define SLOT_SIZE                         (32U)

/* Word size to send/receive data. Word size <= Slot size */
#define WORD_SIZE                         (32U)

/* Number of channels, L & R */
#define NUM_I2S_CHANNELS                  (2U)

/* Number of samples to be used per audio buffer */
#define NUM_SAMPLES_PER_AUDIO_BUF         (20U)

/* Number of buffers used per tx/rx */
#define NUM_BUF                           (3U)

/* Number of linked parameter set used per tx/rx */
#define NUM_PAR                           (1U)

/* Specify where the parameter set starting is */
#define PAR_ID_START                      (40U)

/* McASP Serializer 0 for Transmit */
#define MCASP_XSER_TX_0                   (2U)

/* McASP Serializer 1 for Receive */
#define MCASP_XSER_RX_0                   (3U)

/*
 ** Below Macros are calculated based on the above inputs
 */

#define I2S_SLOTS                         ((1 << NUM_I2S_CHANNELS) - 1)  //1<<2 - 1 = 3

#define BYTES_PER_SAMPLE                  ((WORD_SIZE >> 3) \
                                           * NUM_I2S_CHANNELS)  //4*2 = 8

#define AUDIO_BUF_SIZE                    (NUM_SAMPLES_PER_AUDIO_BUF \
                                           * BYTES_PER_SAMPLE)  //20*8 = 160

/*
 ** Definitions which are configurable depending on the core to be used(ARM here)
 */
#define EDMA3_CHA_MCASP_RX               (0)
#define EDMA3_CHA_MCASP_TX               (1)

#define EDMA3_CC_QUEUE                    (0U)

#define TX_DMA_INT_ENABLE                 (EDMA3CC_OPT_TCC_SET            \
                                               (EDMA3_CHA_MCASP_TX) | (1  \
                                                                       << \
                                                                       EDMA_TPCC_OPT_TCINTEN_SHIFT))
#define RX_DMA_INT_ENABLE                 (EDMA3CC_OPT_TCC_SET            \
                                               (EDMA3_CHA_MCASP_RX) | (1  \
                                                                       << \
                                                                       EDMA_TPCC_OPT_TCINTEN_SHIFT))

#define PAR_RX_START                      (PAR_ID_START)
#define PAR_TX_START                      (PAR_RX_START + NUM_PAR)

/*
 ** Definitions which are not configurable
 */
#define SIZE_PARAMSET                     (32U)
#define OPT_FIFO_WIDTH                    (0x02 << 8U)

/*
 ** Definitions which are configurable depending on the application requirement
 */
#define MCASP_ACLKX_CLKXDIV_VALUE         (0x3U)
#define MCASP_AHCLKX_HCLKXDIV_VALUE       (0x5U)

#define MCASP_ACLKR_CLKRDIV_VALUE         (0x3U)
#define MCASP_AHCLKR_HCLKRDIV_VALUE       (0x5U)

/* ========================================================================== */
/*                          Function prototypes                              */
/* ========================================================================== */
static void I2SDMAParamInit(void);
static void McASPI2SConfigure(void);
static void I2SDataTxActivate(void);

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */
/*
 ** Transmit buffers. If any new buffer is to be added, define it here and
 ** update the NUM_BUF.
 */
static uint8_t txBuf0[AUDIO_BUF_SIZE];
static uint8_t txBuf1[AUDIO_BUF_SIZE];
static uint8_t txBuf2[AUDIO_BUF_SIZE];

static uint8_t rxBuf0[AUDIO_BUF_SIZE];
static uint8_t rxBuf1[AUDIO_BUF_SIZE];
static uint8_t rxBuf2[AUDIO_BUF_SIZE];

/* Array of transmit buffer pointers */
static uint32_t const txBufPtr[NUM_BUF] =
        { (uint32_t) txBuf0, (uint32_t) txBuf1, (uint32_t) txBuf2 };
static uint32_t const rxBufPtr[NUM_BUF] =
        { (uint32_t) rxBuf0, (uint32_t) rxBuf1, (uint32_t) rxBuf2 };
/*
 ** Default paRAM for Transmit section. This will be transmitting from
 ** a loop buffer.
 */
static EDMA3CCPaRAMEntry const txDefaultPar = {
        (uint32_t) (OPT_FIFO_WIDTH), /* Opt field */
        (uint32_t) txBuf0, /* source address */
        (uint16_t) (BYTES_PER_SAMPLE), /* aCnt */
        (uint16_t) (NUM_SAMPLES_PER_AUDIO_BUF), /* bCnt */
        (uint32_t) (SOC_MCASP_BASE), /* dest address */
        (uint16_t) (BYTES_PER_SAMPLE), /* source bIdx */
        (uint16_t) (0), /* dest bIdx */
        (uint16_t) (PAR_TX_START * SIZE_PARAMSET), /* link address */
        (uint16_t) (NUM_SAMPLES_PER_AUDIO_BUF), /* bCnt reload value */
        (uint16_t) (0), /* source cIdx */
        (uint16_t) (0), /* dest cIdx */
        (uint16_t) (1) /* cCnt */
};

static EDMA3CCPaRAMEntry const rxDefaultPar = {
        (uint32_t) (OPT_FIFO_WIDTH), /* Opt field */
        (uint32_t) (SOC_MCASP_BASE), /* source address */
        (uint16_t) (BYTES_PER_SAMPLE), /* aCnt */
        (uint16_t) (NUM_SAMPLES_PER_AUDIO_BUF), /* bCnt */
        (uint32_t) rxBuf0, /* dest address */
        (uint16_t) (0), /* source bIdx */
        (uint16_t) (BYTES_PER_SAMPLE), /* dest bIdx */
        (uint16_t) (PAR_RX_START * SIZE_PARAMSET), /* link address */
        (uint16_t) (NUM_SAMPLES_PER_AUDIO_BUF), /* bCnt reload value */
        (uint16_t) (0), /* source cIdx */
        (uint16_t) (0), /* dest cIdx */
        (uint16_t) (1) /* cCnt */
};

/*
 ** Initializes the DMA parameters.
 ** The TX basic paRAM set (channel) is 12.
 **
 ** The TX paRAM sets will be initialized to transmit from the loop buffer.
 ** The size of the loop buffer can be configured.
 ** The transfer completion interrupt will not be enabled for paRAM set 1;
 ** paRAM set 1 will be linked to linked paRAM set starting (PAR_TX_START) of TX.
 ** All other paRAM sets will be linked to itself.
 ** and further transmission only happens via linked paRAM set.
 ** For example, if the PAR_TX_START value is 72, and the number of paRAMS is 2,
 ** So transmission paRAM set linking will be initialized as 1-->72-->73, 73->73.
 */
static void I2SDMAParamInit(void)
{
    EDMA3CCPaRAMEntry paramSet;

    /* Initialize the 0th paRAM set for receive */
    memset(rxBuf0, 0, AUDIO_BUF_SIZE);
    memcpy(&paramSet, &rxDefaultPar, SIZE_PARAMSET - 2);

    EDMA3SetPaRAM(CSL_DSP_DSP_EDMA_CC_REGS, EDMA3_CHA_MCASP_RX, &paramSet);

    memcpy(&paramSet, &rxDefaultPar, SIZE_PARAMSET - 2);
    /* further paramsets, enable interrupt */
    paramSet.opt |= RX_DMA_INT_ENABLE;
    paramSet.destAddr = rxBufPtr[0];
    paramSet.linkAddr = (PAR_RX_START * SIZE_PARAMSET);
    paramSet.bCnt = NUM_SAMPLES_PER_AUDIO_BUF;

    EDMA3SetPaRAM(CSL_DSP_DSP_EDMA_CC_REGS, PAR_RX_START, &paramSet);

    /* Initialize TX Buffers  */

    memset(txBuf0, 0xf1, AUDIO_BUF_SIZE);

    /* Initialize the 1st paRAM set for transmit */
    memcpy(&paramSet, &txDefaultPar, SIZE_PARAMSET - 2);

    EDMA3SetPaRAM(CSL_DSP_DSP_EDMA_CC_REGS, EDMA3_CHA_MCASP_TX, &paramSet);

    memcpy(&paramSet, &txDefaultPar, SIZE_PARAMSET - 2);
    /* Enable Intr for Link Channel */
    paramSet.opt |= TX_DMA_INT_ENABLE;
    paramSet.srcAddr = txBufPtr[0];
    paramSet.linkAddr = (PAR_TX_START * SIZE_PARAMSET);
    EDMA3SetPaRAM(CSL_DSP_DSP_EDMA_CC_REGS, (PAR_TX_START), &paramSet);
}

void BufferTxDMAActivate(void)
{
    EDMA3CCPaRAMEntry paramSet;

    static uint8_t tmpvalue = 0;

//    memset(txBuf0, tmpvalue++, AUDIO_BUF_SIZE);

    /* Initialize the 1st paRAM set for transmit */
    memcpy(&paramSet, &txDefaultPar, SIZE_PARAMSET - 2);

    EDMA3SetPaRAM(CSL_DSP_DSP_EDMA_CC_REGS, EDMA3_CHA_MCASP_TX, &paramSet);
    memcpy(&paramSet, &txDefaultPar, SIZE_PARAMSET - 2);
    /* Enable Intr for Link Channel */
    paramSet.opt |= TX_DMA_INT_ENABLE;

    paramSet.srcAddr = (uint32_t) txBuf0;
    paramSet.linkAddr = ((PAR_TX_START) * SIZE_PARAMSET);
    EDMA3SetPaRAM(CSL_DSP_DSP_EDMA_CC_REGS, (PAR_TX_START), &paramSet);

}

static void BufferRxDMAActivate(void)
{
    EDMA3CCPaRAMEntry paramSet;
    static uint8_t tmpvalue = 0;
//    memset(rxBuf0, 0, AUDIO_BUF_SIZE);
    /* Initialize the 0th paRAM set for receive */
    memcpy(&paramSet, &rxDefaultPar, SIZE_PARAMSET - 2);

    EDMA3SetPaRAM(CSL_DSP_DSP_EDMA_CC_REGS, EDMA3_CHA_MCASP_RX, &paramSet);

    memcpy(&paramSet, &rxDefaultPar, SIZE_PARAMSET - 2);

    /* further paramsets, enable interrupt */
    paramSet.opt |= RX_DMA_INT_ENABLE;

    paramSet.destAddr = (uint32_t) rxBuf0;
    paramSet.linkAddr = ((PAR_RX_START) * SIZE_PARAMSET);
    EDMA3SetPaRAM(CSL_DSP_DSP_EDMA_CC_REGS, (PAR_RX_START), &paramSet);

}

/*
 ** Configures the McASP Transmit Section in I2S mode.
 */
static void McASPI2SConfigure(void)
{
    McASPTxReset(SOC_MCASP_CFG_BASE);
    McASPRxReset(SOC_MCASP_CFG_BASE);

    /* Enable the FIFOs for DMA transfer */
    McASPWriteFifoEnable(SOC_MCASP_CFG_BASE, 1, 1);
    McASPReadFifoEnable(SOC_MCASP_CFG_BASE, 1, 1);

    /* Set I2S format in the transmitter/receiver format units */
    McASPTxFmtI2SSet(SOC_MCASP_CFG_BASE, WORD_SIZE, SLOT_SIZE,
    MCASP_TX_MODE_DMA);
    McASPRxFmtI2SSet(SOC_MCASP_CFG_BASE, WORD_SIZE, SLOT_SIZE,
    MCASP_RX_MODE_DMA);

    McASPTxFrameSyncCfg(SOC_MCASP_CFG_BASE, 2, MCASP_TX_FS_WIDTH_WORD,
    MCASP_TX_FS_EXT_BEGIN_ON_FALL_EDGE |
    MCASP_TX_FS_INTERNAL);
    McASPRxFrameSyncCfg(SOC_MCASP_CFG_BASE, 2, MCASP_RX_FS_WIDTH_WORD,
    MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE |
    MCASP_RX_FS_INTERNAL);

    /* configure the clock for transmitter */
    McASPTxClkCfg(SOC_MCASP_CFG_BASE, MCASP_TX_CLK_INTERNAL,
                  ((MCASP_ACLKX_CLKXDIV_VALUE &
                  MCASP_ACLKXCTL_CLKXDIV_MASK) >>
                  MCASP_ACLKXCTL_CLKXDIV_SHIFT),
                  ((MCASP_AHCLKX_HCLKXDIV_VALUE &
                  MCASP_AHCLKXCTL_HCLKXDIV_MASK) >>
                  MCASP_AHCLKXCTL_HCLKXDIV_SHIFT));

    McASPTxClkPolaritySet(SOC_MCASP_CFG_BASE, MCASP_TX_CLK_POL_FALL_EDGE);

    McASPTxClkCheckConfig(SOC_MCASP_CFG_BASE, MCASP_TX_CLKCHCK_DIV32, 0x00,
                          0xFF);

    McASPRxClkCfg(SOC_MCASP_CFG_BASE, MCASP_RX_CLK_INTERNAL,
                  ((MCASP_ACLKR_CLKRDIV_VALUE &
                  MCASP_ACLKRCTL_CLKRDIV_MASK) >>
                  MCASP_ACLKRCTL_CLKRDIV_SHIFT),
                  ((MCASP_AHCLKR_HCLKRDIV_VALUE &
                  MCASP_AHCLKRCTL_HCLKRDIV_MASK) >>
                  MCASP_AHCLKRCTL_HCLKRDIV_SHIFT));

    McASPRxClkPolaritySet(SOC_MCASP_CFG_BASE, MCASP_RX_CLK_POL_FALL_EDGE);

    McASPRxClkCheckConfig(SOC_MCASP_CFG_BASE, MCASP_RX_CLKCHCK_DIV32, 0x00,
                          0xFF);

    /* Enable synchronization of RX and TX sections  */
    McASPTxRxClkSyncEnable(SOC_MCASP_CFG_BASE);
//    McASPTxRxClkSyncDisable(SOC_MCASP_CFG_BASE);

    /* Enable the transmitter/receiver slots. I2S uses 2 slots */
    McASPTxTimeSlotSet(SOC_MCASP_CFG_BASE, I2S_SLOTS);
    McASPRxTimeSlotSet(SOC_MCASP_CFG_BASE, I2S_SLOTS);

    /*
     ** Set the serializers
     */
    McASPSerializerTxSet(SOC_MCASP_CFG_BASE, MCASP_XSER_TX_0);
    McASPSerializerRxSet(SOC_MCASP_CFG_BASE, MCASP_XSER_RX_0);

    /*
     ** Configure the McASP pins
     ** Output - Frame Sync, Clock, Serializer Rx and Serializer Tx
     **          (Clocks generated internally)
     */
//    McASPPinMcASPSet(SOC_MCASP_CFG_BASE, 0xFFFFFFFF);
    McASPPinMcASPSet(
            SOC_MCASP_CFG_BASE,
            (MCASP_PIN_AFSR |
            MCASP_PIN_ACLKR | MCASP_PIN_AFSX |
            MCASP_PIN_AHCLKX |
            MCASP_PIN_ACLKX |
            MCASP_PIN_AMUTE | MCASP_PIN_AXR(MCASP_XSER_TX_0)
                    | MCASP_PIN_AXR(MCASP_XSER_RX_0)));

    McASPPinDirInputSet(SOC_MCASP_CFG_BASE, MCASP_PIN_AFSR);
    McASPPinDirInputSet(SOC_MCASP_CFG_BASE, MCASP_PIN_ACLKR);

    McASPPinDirOutputSet(SOC_MCASP_CFG_BASE, MCASP_PIN_AFSX);

    /* Configure high clock as Output */
    McASPPinDirOutputSet(SOC_MCASP_CFG_BASE, MCASP_PIN_AHCLKX);

    McASPPinDirOutputSet(SOC_MCASP_CFG_BASE, MCASP_PIN_ACLKX);

    /* Both Serializers used to output data out */
    McASPPinDirOutputSet(SOC_MCASP_CFG_BASE, MCASP_PIN_AXR(MCASP_XSER_TX_0));
    McASPPinDirInputSet(SOC_MCASP_CFG_BASE, MCASP_PIN_AXR(MCASP_XSER_RX_0));

    /* Enable error interrupts for McASP */
    McASPTxIntEnable(
            SOC_MCASP_CFG_BASE,
            MCASP_TX_DMAERROR | MCASP_TX_CLKFAIL | MCASP_TX_SYNCERROR
                    | MCASP_TX_UNDERRUN);

    McASPRxIntEnable(
            SOC_MCASP_CFG_BASE,
            MCASP_RX_DMAERROR | MCASP_RX_CLKFAIL | MCASP_RX_SYNCERROR
                    | MCASP_RX_OVERRUN);
}

/*
 ** Activates the data transmission/reception
 ** The DMA parameters shall be ready before calling this function.
 */
static void I2SDataTxActivate(void)
{
    /* Start the clocks */
    McASPRxClkStart(SOC_MCASP_CFG_BASE, MCASP_RX_CLK_INTERNAL);
    McASPTxClkStart(SOC_MCASP_CFG_BASE, MCASP_TX_CLK_INTERNAL);

    /* Enable EDMA for the transfer */
    EDMA3EnableTransfer(CSL_DSP_DSP_EDMA_CC_REGS, EDMA3_CHA_MCASP_RX,
    EDMA3_TRIG_MODE_EVENT);
    EDMA3EnableTransfer(CSL_DSP_DSP_EDMA_CC_REGS, EDMA3_CHA_MCASP_TX,
    EDMA3_TRIG_MODE_EVENT);

    /* Activate the  serializers */
    McASPRxSerActivate(SOC_MCASP_CFG_BASE);
    McASPTxSerActivate(SOC_MCASP_CFG_BASE);

    /* make sure that the XDATA bit is cleared to zero */
    while (McASPRxStatusGet(SOC_MCASP_CFG_BASE) & MCASP_RX_STAT_DATAREADY )
        ;
    while (McASPTxStatusGet(SOC_MCASP_CFG_BASE) & MCASP_TX_STAT_DATAREADY )
        ;

    /* Activate the state machines */
    McASPRxEnable(SOC_MCASP_CFG_BASE);
    McASPTxEnable(SOC_MCASP_CFG_BASE);
}

static void McASPRxDMAComplHandler(void)
{
    BufferRxDMAActivate();
//    static uint32_t cnt = 0;
//    uint32_t status = McASPRxBufRead(SOC_MCASP_CFG_BASE, MCASP_XSER_RX_0);
//    if (status != 0)
//    {
//        cnt++;
//        if ((cnt % 20 == 0))
//        {
//            System_printf("McASPRxBufRead:0x%x,cnt:%d\r\n", status, cnt);
//            memset(txBuf0, cnt, AUDIO_BUF_SIZE);
//        }
//    }
}

/*
 ** This function will be called once transmit DMA is completed
 */
static void McASPTxDMAComplHandler(void)
{
    BufferTxDMAActivate();
}

void Edma3ComplHandlerIsr(void *dummy)
{
    /* Check if receive DMA completed */
    if (EDMA3GetIntrStatus(CSL_DSP_DSP_EDMA_CC_REGS)
            & (1 << EDMA3_CHA_MCASP_RX))
    {
        /* Clear the interrupt status for the 0th channel */
        EDMA3ClrIntr(CSL_DSP_DSP_EDMA_CC_REGS, EDMA3_CHA_MCASP_RX);
        McASPRxDMAComplHandler();
    }

    /* Check if transmit DMA completed */
    if (EDMA3GetIntrStatus(CSL_DSP_DSP_EDMA_CC_REGS)
            & (1 << EDMA3_CHA_MCASP_TX))
    {
        /* Clear the interrupt status for the first channel */
        EDMA3ClrIntr(CSL_DSP_DSP_EDMA_CC_REGS, EDMA3_CHA_MCASP_TX);
        McASPTxDMAComplHandler();
//        System_printf("Edma3ComplHandlerIsr...EDMA3_CHA_MCASP_TX\r\n");
    }
}

void Edma3ErrorHandlerIsr(void *dummy)
{
    System_printf("Edma3ErrorHandlerIsr...\r\n");
}

/*
 ** The main function. Application starts here.
 */
int mcasp_test_Task(void)
{
    uint32_t loopHere = 1, status = 0;
    unsigned short parToSend;
    unsigned short parToLink;

    EDMAsetRegion(0);
    EDMA3Init(CSL_DSP_DSP_EDMA_CC_REGS, EDMA3_CC_QUEUE);

    /* Request EDMA channels */
    EDMA3RequestChannel(CSL_DSP_DSP_EDMA_CC_REGS,
    EDMA3_CHANNEL_TYPE_DMA,
                        EDMA3_CHA_MCASP_TX,
                        EDMA3_CHA_MCASP_TX,
                        EDMA3_CC_QUEUE);
    EDMA3RequestChannel(CSL_DSP_DSP_EDMA_CC_REGS,
    EDMA3_CHANNEL_TYPE_DMA,
                        EDMA3_CHA_MCASP_RX,
                        EDMA3_CHA_MCASP_RX,
                        EDMA3_CC_QUEUE);

    /* Initialize the DMA parameters */
    I2SDMAParamInit();

    /* Configure the McASP for I2S */
    McASPI2SConfigure();

    /* Activate the audio transmission and reception */
    I2SDataTxActivate();

    /*
     ** Loop forever.
     */
    int j = 0;
    Task_sleep(1000);

    while (loopHere)
    {

        if (rxBuf0[0] != 0 || rxBuf0[0] != 0)
        {
            for (j = 0; j < AUDIO_BUF_SIZE; j++)
            {
                System_printf("rxBuf0[%d]:0x%x\r\n", j, rxBuf0[j]);
//            System_printf("rxBuf1[%d]:0x%x\r\n", j, rxBuf1[j]);
                Task_sleep(1);
            }
        }
        else
        {
            status = McASPTxStatusGet(SOC_MCASP_CFG_BASE); //0x4846 80c0
            if (status & 0x100)
                System_printf("Txstatus:0x%x\r\n", status);
            status = McASPRxStatusGet(SOC_MCASP_CFG_BASE); //0x4846 8080
            if (status & 0x100)
                System_printf("Rxstatus:0x%x\r\n", status);
        }
//        status = McASPRxBufRead(SOC_MCASP_CFG_BASE,MCASP_XSER_RX_0);
//        System_printf("McASPRxBufRead:0x%x\r\n", status);
        memset(rxBuf0, 0, AUDIO_BUF_SIZE);
        memset(rxBuf1, 0, AUDIO_BUF_SIZE);

//        memset(txBuf0, 0, AUDIO_BUF_SIZE);
//        BufferTxDMAActivate();
//        BufferRxDMAActivate();
        Task_sleep(1);
    }

    return 0;
}

/***************************** End Of File ***********************************/