系统：
stm32为ti模式的spi主机，dsp为spi从机，两者都使用dma，
具体问题：
1.主机发送从机接收：上电后，主机第一次发送1024个16位的数据，从机(dsp)接收到1023个数据(这些数据没有问题)，在下一次传输开始后，接收到最后一个数据，并产生中断，并在处理完中断事件后，进行下一次的接收，即再次接收1023点，后等待下一次数据传输；经过验证，最后一位数据确实为上一次发送的最后一位数据。
2.从机发送主机接收：上电后，在主机开启第一次发送后，从机开启发送，从主机的接收数据中可以看出，其与发送结果一致；当开始下一次传输时，主机先会接收到上一次传输的两个尾部数据，并且其中的第二个数据为0x0000，其余数据值正常，出现位置依次错位；在进行第三次传输时，主机先会接收到上一次传输的三个尾部数据，其余数据值正常，出现位置依次错位；应该也与‘1’中的原因类似，相当于两次发送产生一次接收，只是错位数据量不同。
3.个人感觉应该是dma配置的问题，希望各位大佬能帮帮忙。
dsp端的代码：
/*
* main.c
*/
#include <stdio.h>
//#define CHIP_5509A
#include <csl.h>
#include <csl_pll.h>
#include <csl_chip.h>
#include <csl_gpio.h>
#include <csl_mcbsp.h>
#include <math.h>
#include <tms320.h>
#include <stdio.h>
#include <csl_dma.h>
#include <csl_irq.h>
#include <dsplib.h>
#define N 1024
#define N2 1024
//---------Global data definition---------
/* Define transmit and receive buffers */
#pragma DATA_SECTION(xmt,".dmaMem")
DATA xmt[N2];
#pragma DATA_SECTION(xmtB,".dmaMem")
DATA xmtB[N2];
#pragma DATA_SECTION(rcv,".dmaMem")
DATA rcv[N];
#pragma DATA_SECTION(rcvB,".dmaMem2")
DATA rcvB[N];
// PLL 初始化结构体
PLL_Config myConfig = {
0, //IAI: the PLL locks using the same process that was underway
//before the idle mode was entered
1, //IOB: If the PLL indicates a break in the phase lock,
//it switches to its bypass mode and restarts the PLL phase-locking
//sequence
24, //PLL multiply value; multiply 24 times
1 //Divide by 2 PLL divide value; it can be either PLL divide value
//(when PLL is enabled), or Bypass-mode divide value
//(PLL in bypass mode, if PLL multiply value is set to 1)
};
//McBSP 对应结构体以及初始化
MCBSP_Config ConfigLoopBack16= {
MCBSP_SPCR1_RMK(
MCBSP_SPCR1_DLB_OFF, /* DLB = 0 */
MCBSP_SPCR1_RJUST_RZF, /* RJUST = 0 */
MCBSP_SPCR1_CLKSTP_NODELAY, /* CLKSTP = 0 */ //MCBSP_SPCR1_CLKSTP_NODELAY
MCBSP_SPCR1_DXENA_NA, /* DXENA = 0 */
MCBSP_SPCR1_ABIS_DISABLE, /* ABIS = 0 */
MCBSP_SPCR1_RINTM_RRDY, /* RINTM = 0 */
0, /* RSYNCER = 0 */
MCBSP_SPCR1_RRST_DISABLE /* RRST = 0 */
),
MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_NO, /* FREE = 0 */
MCBSP_SPCR2_SOFT_NO, /* SOFT = 0 */
MCBSP_SPCR2_FRST_FSG, /* FRST = 0 */
MCBSP_SPCR2_GRST_CLKG, /* GRST = 0 */
MCBSP_SPCR2_XINTM_XRDY, /* XINTM = 0 */
0, /* XSYNCER = N/A */
MCBSP_SPCR2_XRST_DISABLE /* XRST = 0 */
),
MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_OF(0), /* RFRLEN1 = 0 */
MCBSP_RCR1_RWDLEN1_16BIT /* RWDLEN1 = 5 */
),
MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_SINGLE, /* RPHASE = 0 */
MCBSP_RCR2_RFRLEN2_OF(0), /* RFRLEN2 = 0 */
MCBSP_RCR2_RWDLEN2_16BIT, /* RWDLEN2 = 0 */
MCBSP_RCR2_RCOMPAND_MSB, /* RCOMPAND = 0 */
MCBSP_RCR2_RFIG_YES, /* RFIG = 0 */
MCBSP_RCR2_RDATDLY_0BIT /* RDATDLY = 0 */
),
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_OF(0), /* XFRLEN1 = 0 */
MCBSP_XCR1_XWDLEN1_16BIT /* XWDLEN1 = 5 */
),
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE, /* XPHASE = 0 */
MCBSP_XCR2_XFRLEN2_OF(0), /* XFRLEN2 = 0 */
MCBSP_XCR2_XWDLEN2_16BIT, /* XWDLEN2 = 0 */
MCBSP_XCR2_XCOMPAND_MSB, /* XCOMPAND = 0 */
MCBSP_XCR2_XFIG_YES, /* XFIG = 0 */
MCBSP_XCR2_XDATDLY_0BIT /* XDATDLY = 0 */
),
MCBSP_SRGR1_RMK(
MCBSP_SRGR1_FWID_OF(1), /* FWID = 1 */
MCBSP_SRGR1_CLKGDV_OF(1) /* CLKGDV = 1 */
),
MCBSP_SRGR2_RMK(
MCBSP_SRGR2_GSYNC_FREE, /* FREE = 0 */
MCBSP_SRGR2_CLKSP_RISING, /* CLKSP = 0 */
MCBSP_SRGR2_CLKSM_INTERNAL, /* CLKSM = 1 */
MCBSP_SRGR2_FSGM_DXR2XSR, /* FSGM = 0 */
MCBSP_SRGR2_FPER_OF(15) /* FPER = 0 */
),
MCBSP_MCR1_DEFAULT,
MCBSP_MCR2_DEFAULT,
MCBSP_PCR_RMK(
MCBSP_PCR_IDLEEN_RESET, /* IDLEEN = 0 */
MCBSP_PCR_XIOEN_SP, /* XIOEN = 0 */
MCBSP_PCR_RIOEN_SP, /* RIOEN = 0 */
MCBSP_PCR_FSXM_EXTERNAL, /* FSXM = 0 */
MCBSP_PCR_FSRM_EXTERNAL, /* FSRM = 0 */
MCBSP_PCR_CLKXM_INPUT, /* CLKXM = 0 */
MCBSP_PCR_CLKRM_OUTPUT, /* CLKRM = 1 */
MCBSP_PCR_SCLKME_NO, /* SCLKME = 0 */
0, /* DXSTAT = N/A */
MCBSP_PCR_FSXP_ACTIVELOW, //LOW =1 /* FSXP = 0 */
MCBSP_PCR_FSRP_ACTIVELOW, /* FSRP = 0 */
MCBSP_PCR_CLKXP_RISING, // RISING /* CLKXP = 0 */ //1;MCBSP_PCR_CLKXP_RISING
MCBSP_PCR_CLKRP_RISING//FALLING /* CLKRP = 0 */ //1
),
MCBSP_RCERA_DEFAULT,
MCBSP_RCERB_DEFAULT,
MCBSP_RCERC_DEFAULT,
MCBSP_RCERD_DEFAULT,
MCBSP_RCERE_DEFAULT,
MCBSP_RCERF_DEFAULT,
MCBSP_RCERG_DEFAULT,
MCBSP_RCERH_DEFAULT,
MCBSP_XCERA_DEFAULT,
MCBSP_XCERB_DEFAULT,
MCBSP_XCERC_DEFAULT,
MCBSP_XCERD_DEFAULT,
MCBSP_XCERE_DEFAULT,
MCBSP_XCERF_DEFAULT,
MCBSP_XCERG_DEFAULT,
MCBSP_XCERH_DEFAULT
};
//DMA
/* Create DMA Receive Side Configuration */
DMA_Config dmaRcvConfig = {
DMA_DMACSDP_RMK(
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_DARAM,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_PERIPH,
DMA_DMACSDP_DATATYPE_16BIT
), /* DMACSDP */
DMA_DMACCR_RMK(
DMA_DMACCR_DSTAMODE_POSTINC,
DMA_DMACCR_SRCAMODE_CONST,
DMA_DMACCR_ENDPROG_ON,
DMA_DMACCR_REPEAT_OFF,/****20220401****/
DMA_DMACCR_AUTOINIT_ON,/****20220401****/
DMA_DMACCR_EN_STOP,
DMA_DMACCR_PRIO_LOW,
DMA_DMACCR_FS_DISABLE,
DMA_DMACCR_SYNC_REVT1
), /* DMACCR */
DMA_DMACICR_RMK(
DMA_DMACICR_BLOCKIE_OFF,
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_ON,
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
), /* DMACICR */
(DMA_AdrPtr)(MCBSP_ADDR(DRR11)), /* DMACSSAL */
0, /* DMACSSAU */
0, /* DMACDSAL */ //在后面进行了赋值
0, /* DMACDSAU */
N, /* DMACEN */
1, /* DMACFN */
0, /* DMACFI */
0 /* DMACEI */
};
/* Create DMA Transmit Side Configuration */
DMA_Config dmaXmtConfig = {
DMA_DMACSDP_RMK(
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_PERIPH,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_DARAM,
DMA_DMACSDP_DATATYPE_16BIT
), /* DMACSDP */
DMA_DMACCR_RMK(
DMA_DMACCR_DSTAMODE_CONST,
DMA_DMACCR_SRCAMODE_POSTINC,
DMA_DMACCR_ENDPROG_ON,
DMA_DMACCR_REPEAT_OFF,/****20220401****/
DMA_DMACCR_AUTOINIT_ON,/****20220401****/
DMA_DMACCR_EN_STOP,
DMA_DMACCR_PRIO_LOW,
DMA_DMACCR_FS_DISABLE,
DMA_DMACCR_SYNC_XEVT1
), /* DMACCR */
DMA_DMACICR_RMK(
DMA_DMACICR_BLOCKIE_OFF,
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_ON,
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
), /* DMACICR */
0, /* DMACSSAL */ //在后面进行了赋值
0, /* DMACSSAU */
(DMA_AdrPtr)(MCBSP_ADDR(DXR11)), /* DMACDSAL */
0, /* DMACDSAU */
N2, /* DMACEN */
1, /* DMACFN */
0, /* DMACFI */
0 /* DMACEI */
};
/* Define a DMA_Handle object to be used with DMA_open function */
DMA_Handle hDmaRcv, hDmaXmt;
/* Define a MCBSP_Handle object to be used with MCBSP_open function */
MCBSP_Handle hMcbsp;
volatile Uint16 receiveComplete = FALSE;
volatile Uint16 transmitComplete = FALSE;
volatile Uint16 rbflg = 0;
Uint16 err = 0;
Uint16 old_intm;
Uint16 xmtEventId, rcvEventId;
Uint16 runtimeX=0,runtimeR=0;
//---------Function prototypes---------
/* Reference start of interrupt vector table */
/* This symbol is defined in file, vectors.s55 */
extern void VECSTART(void);
/* Protoype for interrupt functions */
interrupt void dmaXmtIsr(void);
interrupt void dmaRcvIsr(void);
void taskFxn(void);
void main(void)
{
Uint16 i;
/* Initialize CSL library - This is REQUIRED !!! */
CSL_init();
/* Set IVPD/IVPH to start of interrupt vector table */
IRQ_setVecs((Uint32)(&VECSTART));
PLL_config(&myConfig);
for (i = 0; i <= N - 1; i++) {
rcv[i] = 0;
rcvB[i] = 0;
}
for (i = 0; i <= N; i++) {
xmt[i] = N-i;
xmtB[i] = N-i;
}
/* Call function to effect transfer */
taskFxn();
}
void taskFxn(void)
{
Uint16 srcAddrHi, srcAddrLo;
Uint16 dstAddrHi, dstAddrLo;
Uint16 i;
/* By default, the TMS320C55xx compiler assigns all data symbols word */
/* addresses. The DMA however, expects all addresses to be byte */
/* addresses. Therefore, we must shift the address by 2 in order to */
/* change the word address to a byte address for the DMA transfer. */
srcAddrHi = (Uint16)(((Uint32)(MCBSP_ADDR(DRR11))) >> 15) & 0xFFFFu;
srcAddrLo = (Uint16)(((Uint32)(MCBSP_ADDR(DRR11))) << 1) & 0xFFFFu;
dstAddrHi = (Uint16)(((Uint32)(rcv)) >> 15) & 0xFFFFu;
dstAddrLo = (Uint16)(((Uint32)(rcv)) << 1) & 0xFFFFu;
dmaRcvConfig.dmacssal = (DMA_AdrPtr)srcAddrLo;
dmaRcvConfig.dmacssau = srcAddrHi;
dmaRcvConfig.dmacdsal = (DMA_AdrPtr)dstAddrLo;
dmaRcvConfig.dmacdsau = dstAddrHi;
srcAddrHi = (Uint16)(((Uint32)(xmt)) >> 15) & 0xFFFFu;
srcAddrLo = (Uint16)(((Uint32)(xmt)) << 1) & 0xFFFFu;
dstAddrHi = (Uint16)(((Uint32)(MCBSP_ADDR(DXR11))) >> 15) & 0xFFFFu;
dstAddrLo = (Uint16)(((Uint32)(MCBSP_ADDR(DXR11))) << 1) & 0xFFFFu;
dmaXmtConfig.dmacssal = (DMA_AdrPtr)srcAddrLo;
dmaXmtConfig.dmacssau = srcAddrHi;
dmaXmtConfig.dmacdsal = (DMA_AdrPtr)dstAddrLo;
dmaXmtConfig.dmacdsau = dstAddrHi;
/* Open DMA channels 4 & 5 and set regs to power on defaults */
hDmaRcv = DMA_open(DMA_CHA4,DMA_OPEN_RESET);
hDmaXmt = DMA_open(DMA_CHA5,DMA_OPEN_RESET);
/* Open MCBSP Port 1 and set registers to their power on defaults */
hMcbsp = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);
/* Get interrupt event associated with DMA receive and transmit */
xmtEventId = DMA_getEventId(hDmaXmt);
rcvEventId = DMA_getEventId(hDmaRcv);
/* Temporarily disable interrupts and clear any pending */
/* interrupts for MCBSP transmit */
old_intm = IRQ_globalDisable();
/* Clear any pending interrupts for DMA channels */
IRQ_clear(xmtEventId);
IRQ_clear(rcvEventId);
/* Enable DMA interrupt in IER register */
IRQ_enable(xmtEventId);
IRQ_enable(rcvEventId);
/* Set Start Of Interrupt Vector Table */
IRQ_setVecs(0x10000);
/* Place DMA interrupt service addresses at associate vector */
IRQ_plug(xmtEventId,&dmaXmtIsr);
IRQ_plug(rcvEventId,&dmaRcvIsr);
/* Write values from configuration structure to DMA control regs */
DMA_config(hDmaRcv,&dmaRcvConfig);
DMA_config(hDmaXmt,&dmaXmtConfig);
/* Write values from configuration structure to MCBSP control regs */
MCBSP_config(hMcbsp, &ConfigLoopBack16);
/* Enable all maskable interrupts */
IRQ_globalEnable();
/* Enable DMA */
DMA_start(hDmaRcv);
DMA_start(hDmaXmt);
/* Start Sample Rate Generator and Enable Frame Sync */
MCBSP_start(hMcbsp,
MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC,
0x30u);
/* Take MCBSP transmit and receive out of reset */
MCBSP_start(hMcbsp,
MCBSP_XMIT_START | MCBSP_RCV_START,
0u);
while(1)
{
/* Wait for DMA transfer to be complete */
while (!receiveComplete){}//等待接收完成
while (!transmitComplete){}//
while(DMA_FGETH(hDmaRcv, DMACCR, ENDPROG));
dstAddrHi = (Uint16)(((Uint32)(rcv)) >> 15) & 0xFFFFu;
dstAddrLo = (Uint16)(((Uint32)(rcv)) << 1) & 0xFFFFu;
DMA_RSETH(hDmaRcv, DMACDSAU, dstAddrHi);
DMA_RSETH(hDmaRcv, DMACDSAL, dstAddrLo);
DMA_RSETH(hDmaRcv, DMACEN,N);
DMA_RSETH(hDmaRcv, DMACFN,1);
DMA_FSETH(hDmaRcv, DMACCR, ENDPROG,1);
while(DMA_FGETH(hDmaXmt, DMACCR, ENDPROG));
for(i=0;i<N2;i++) xmt[i]=xmt[i]+8;
srcAddrHi = (Uint16)(((Uint32)(xmt)) >> 15) & 0xFFFFu;
srcAddrLo = (Uint16)(((Uint32)(xmt)) << 1) & 0xFFFFu;
DMA_RSETH(hDmaXmt, DMACSSAU, srcAddrHi);
DMA_RSETH(hDmaXmt, DMACSSAL, srcAddrLo);
DMA_RSETH(hDmaXmt, DMACEN,N2);
DMA_RSETH(hDmaXmt, DMACFN,1);
DMA_FSETH(hDmaXmt, DMACCR, ENDPROG,1);
receiveComplete = FALSE;
transmitComplete = FALSE;
}
/* Restore status of global interrupt enable flag */
IRQ_globalRestore(old_intm);
/* We're done with MCBSP and DMA , so close them */
MCBSP_close(hMcbsp);
DMA_close(hDmaRcv);
DMA_close(hDmaXmt);
}
interrupt void dmaXmtIsr(void) {
runtimeX++;//记录中断触发次数
transmitComplete = TRUE;
DMA_FSETH(hDmaXmt, DMACSR, FRAME,0);
}
interrupt void dmaRcvIsr(void) {
runtimeR++;
receiveComplete = TRUE;
DMA_FSETH(hDmaRcv, DMACSR, FRAME,0);
}
