TMS320C6748: MCBSP使用EDMA3传输音频， 无法产生EDMA中断

Hi:

        我目前使用EDMA完成，MCBSP的传输， 遇到无法检测到EDMA中断的问题。MCBSP配置为 IIS主模式 。

MCBSP 和 EDMA配置如下描述， 时钟用示波器可以正常量到。

目前EDMA 无中断产生（CC0_INT）, 中断函数正常（ 与MCASP中断属于同一中断， MCASP上验证过没有问题 ）？

问题1： 如何判断是MCBSP REVT或者XEVT 发送的问题， 还是EDMA配置通道的问题。

配置如下：

1. MCBSP  

    //reset
	MCBSP->SPCR.bit.uFREE = 1;
	MCBSP->SPCR.bit.uSOFT = 1;

	MCBSP->SPCR.bit.FRST = 0;
	MCBSP->SPCR.bit.GRST = 0;
	MCBSP->SPCR.bit.XRST = 0;
	MCBSP->SPCR.bit.RRST = 0;
	
	//fifo config

	MCBSP_RFIFOCTL |= 1;			
	MCBSP_RFIFOCTL |= 1<<8;

	MCBSP_RFIFOCTL |= 0x00010000;
	while (!CHKBIT(MCBSP_RFIFOCTL, 0x00010000)) {} 
	

	MCBSP_WFIFOCTL |= 1;
	MCBSP_WFIFOCTL |= 1<<8;

	MCBSP_WFIFOCTL |= 0x00010000;
	while (!CHKBIT(MCBSP_WFIFOCTL, 0x00010000)) {} 

	//clock 
	MCBSP->PCR.bit.CLKRP = 0; //falling edge
	MCBSP->PCR.bit.CLKXP = 0;

	
	MCBSP->PCR.bit.FSRP = 0;  //falling edge
	MCBSP->PCR.bit.FSXP = 0;

	

	#if MCBSP_HOST
	MCBSP->PCR.bit.CLKRM = 1;  //internal clock source
	MCBSP->PCR.bit.CLKXM = 1;  //internal clock source
	
	MCBSP->PCR.bit.FSRM = 1;  //internal clock source
	MCBSP->PCR.bit.FSXM = 1;  //internal clock source

	MCBSP->SRGR.bit.FSGM = 1;
	MCBSP->SRGR.bit.FPER = 63;
	MCBSP->SRGR.bit.FWID = 31;  //32bits trans width , 16 bit avilable
	MCBSP->SRGR.bit.CLKGDV = 75;

	MCBSP->SRGR.bit.CLKSM = 1;
	MCBSP->PCR.bit.SCLKME = 0;
	#else
	MCBSP->PCR.bit.CLKRM = 0;  //external clock source
	MCBSP->PCR.bit.CLKXM = 0;  //external clock source
	
	MCBSP->PCR.bit.FSRM = 0;  //external clock source
	MCBSP->PCR.bit.FSXM = 0;  //external clock source
	#endif

	//format
	
	MCBSP->RCR.bit.RPHASE = 1; //Dual Phase Receive
	MCBSP->RCR.bit.RWDLEN1 = 5;
	MCBSP->RCR.bit.RWDLEN2 = 5;
	MCBSP->RCR.bit.RDATDLY = 1;

	MCBSP->RCR.bit.RFRLEN1 = 0;
	MCBSP->RCR.bit.RFRLEN2 = 0;

	MCBSP->XCR.bit.XPHASE = 1; //Dual Phase Receive
	MCBSP->XCR.bit.XWDLEN1 = 5;
	MCBSP->XCR.bit.XWDLEN2 = 5;
	MCBSP->XCR.bit.XDATDLY = 1;

	MCBSP->XCR.bit.XFRLEN1 = 0;
	MCBSP->XCR.bit.XFRLEN2 = 0;

	MCBSP->XCR.bit.XCOMPAND = 0;
	//MCBSP->XCR.bit.XFIG = 1;

	delay_ms(1);
	
	MCBSP->SPCR.bit.GRST = 1;
	while (!CHKBIT(MCBSP->SPCR.bit.GRST, 1)) {}

	delay_ms(1);

	MCBSP->SPCR.bit.XRST = 1;
	while (!CHKBIT(MCBSP->SPCR.bit.XRST, 1)) {}

	delay_ms(1);
	MCBSP->SPCR.bit.XRST = 0;

2. EDMA_CC0

    //Init 
    edmaCcRegs->ECR 	 = 0xFFFFFFFF;
	edmaCcRegs->EECR	 = 0xFFFFFFFF;
	edmaCcRegs->ICR 	 = 0xFFFFFFFF;
	edmaCcRegs->IECR	 = 0xFFFFFFFF;
	edmaCcRegs->EMCR	 = 0xFFFFFFFF;
	edmaCcRegs->CCERRCLR = 0xFFFFFFFF;
	edmaCcRegs->SECR	 = 0xFFFFFFFF; 
	
	//config 
	//1<<4(MCBSP1 Recveive envent)
	//1<<5(MCBSP1 Transmit envent)
	edmaCcRegs->DRA[1].DRAE |= 0x00000030; 
	//channel queue 0 for E4 & E5
	edmaCcRegs->DMAQNUM[0]  |= 0x00110000;
	
	//config Paramset 
	//rcv_ping : 
	aCnt = 4 bCnt = 2 CCnt = 192
	
	srcBIdx = 0;//aCount;
	dstBIdx = cCount*aCount;
	srcCIdx = 0;//bCount*aCount;
	dstCIdx = aCount-(bCount-1)*dstBIdx;
	
	SRC: 0x01D11000  (MCBSP1. DRR)
	DST: IRAM    
	
	//xmt
	aCnt = 4 bCnt = 2 CCnt = 192
	
	srcBIdx = 0;//aCount;
	dstBIdx = cCount*aCount;
	srcCIdx = 0;//bCount*aCount;
	dstCIdx = aCount-(bCount-1)*dstBIdx;
	
	srcBIdx = cCount*aCount;//aCount;
	dstBIdx = 0;
	srcCIdx = aCount-(bCount-1)*dstBIdx;//bCount*aCount;
	dstCIdx = 0;
	
	SRC: IRAM
	DST:  0x01D11004  (MCBSP1. DXR)
	
	

3.EDMA 使能 

    //EDMA Start
    edmaCcRegs->EECR = 0xff;
	edmaCcRegs->ECR  = 0xff;
	edmaCcRegs->EER  = 0xff;
	edmaCcRegs->EESR = 0xff;
	edmaCcRegs->IESR = 0xff;

4. MCBSP 使能

    MCBSP->SPCR.bit.XRST = 1;
	while (!CHKBIT(MCBSP->SPCR.bit.XRST, 1)) {}

	MCBSP->SPCR.bit.RRST = 1;
	while (!CHKBIT(MCBSP->SPCR.bit.RRST, 1)) {}

	while(!(MCBSP->SPCR.bit.XEMPTY == 0)){}	
	MCBSP->DXR = 0;

	MCBSP->SPCR.bit.FRST = 1;
	/*