目前在AM64XEVM板卡运行mcu_plus_sdk_am64x_08_04_00_17提供的enet_lwip_icssg用例时, UDMA无法触发中断, 网卡收包完全依赖timer触发, 请问如何解决? 我使用测试方法是通过在中断处理函数中添加标志位, 以及修改timer的触发时间,来确定中断没是否触发.
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我在“C:\ti\mcu_plus_sdk_am64x_08_04_00_17”安装了“mcu_plus_sdk_am64x_08_04_00_17”
在“C:\ti\ccs1200”安装了 CCS12
导入“C:\ti\mcu_plus_sdk_am64x_08_04_00_17\examples\networking\lwip\enet_lwip_icssg\am64x-evm\r5fss0-0_freertos\ti-arm-clang”
使用 SBL NULL 配置电路板。
构建并加载应用程序,我得到了一下日志。请问我们的设置相同还是我与您的设置不同呢?
=====================================================================
Starting NULL Bootloader ...
DMSC Firmware Version 8.4.7--v08.04.07 (Jolly Jellyfi
DMSC Firmware revision 0x8
DMSC ABI revision 3.1
INFO: Bootloader_runCpu:155: CPU r5f1-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU r5f1-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU m4f0-0 is initialized to 400000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU a530-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU a530-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_loadSelfCpu:207: CPU r5f0-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_loadSelfCpu:207: CPU r5f0-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_runSelfCpu:217: All done, reseting self ...
==========================
ENET LWIP App
==========================
Enabling clocks!
Mdio_open: MDIO Manual_Mode enabled
EnetPhy_bindDriver: PHY 15: OUI:080028 Model:0f Ver:01 <-> 'dp83869' : OK
PHY 3 is alive
PHY 15 is alive
Starting lwIP, local interface IP is dhcp-enabled
Host MAC address: 70:ff:76:1e:9c:a8
[LWIPIF_LWIP] Enet has been started successfully
[LWIPIF_LWIP] NETIF INIT SUCCESS
status_callback==UP, local interface IP is 0.0.0.0
UDP server listening on port 5001
Icssg_handleLinkUp: icssg1-1: Port 1: Link up: 1-Gbps Full-Duplex
link_callback==UP
5.147s : CPU load = 2.50 %
10.147s : CPU load = 2.11 %
15.147s : CPU load = 2.10 %
20.147s : CPU load = 2.10 %
25.147s : CPU load = 2.10 %
30.147s : CPU load = 2.10 %
35.147s : CPU load = 2.11 %
40.147s : CPU load = 2.11 %
45.147s : CPU load = 2.10 %
50.147s : CPU load = 2.10 %
55.147s : CPU load = 2.10 %
60.147s : CPU load = 2.10 %
65.147s : CPU load = 2.10 %
70.147s : CPU load = 2.11 %
75.147s : CPU load = 2.11 %
80.147s : CPU load = 2.11 %
85.147s : CPU load = 2.10 %
90.147s : CPU load = 2.10 %
95.147s : CPU load = 2.10 %
100.147s : CPU load = 2.10 %
105.147s : CPU load = 2.10 %
110.147s : CPU load = 2.10 %
115.147s : CPU load = 2.10 %
120.147s : CPU load = 2. 9 %
125.147s : CPU load = 2.10 %
130.147s : CPU load = 2.11 %
135.147s : CPU load = 2.10 %
140.147s : CPU load = 2.10 %
145.147s : CPU load = 2.11 %
150.147s : CPU load = 2.11 %
155.147s : CPU load = 2.11 %
160.147s : CPU load = 2.11 %
165.147s : CPU load = 2.10 %
170.147s : CPU load = 2.11 %
175.147s : CPU load = 2.11 %
180.147s : CPU load = 2.11 %
185.147s : CPU load = 2.11 %
190.147s : CPU load = 2.11 %
195.147s : CPU load = 2.10 %
200.147s : CPU load = 2.10 %
205.147s : CPU load = 2.10 %
210.147s : CPU load = 2.10 %
215.147s : CPU load = 2.10 %
220.147s : CPU load = 2.11 %
225.147s : CPU load = 2.11 %
230.147s : CPU load = 2.10 %
235.147s : CPU load = 2.10 %
240.147s : CPU load = 2.10 %
245.147s : CPU load = 2.10 %
status_callback==UP, local interface IP is 169.254.169.156
250.147s : CPU load = 2.13 %
255.147s : CPU load = 2.11 %
260.147s : CPU load = 2.10 %
=====================================================================
tarting NULL Bootloader ...
DMSC Firmware Version 8.4.7--v08.04.07 (Jolly Jellyfi
DMSC Firmware revision 0x8
DMSC ABI revision 3.1
INFO: Bootloader_runCpu:155: CPU r5f1-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU r5f1-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU m4f0-0 is initialized to 400000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU a530-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU a530-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_loadSelfCpu:207: CPU r5f0-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_loadSelfCpu:207: CPU r5f0-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_runSelfCpu:217: All done, reseting self ...
==========================
ENET LWIP App
==========================
Enabling clocks!
Mdio_open:282
EnetPhy_bindDriver:1718
PHY 3 is alive
PHY 15 is alive
Starting lwIP, local interface IP is dhcp-enabled
Host MAC address: 70:ff:76:1e:2a:d9
[LWIPIF_LWIP] Enet has been started successfully
[LWIPIF_LWIP] NETIF INIT SUCCESS
status_callback==UP, local interface IP is 0.0.0.0
UDP server listening on port 5001
5.135s : CPU load = 1.17 %
10.135s : CPU load = 0.58 %
15.135s : CPU load = 0.48 %
20.135s : CPU load = 0.59 %
25.135s : CPU load = 0.49 %
30.135s : CPU load = 0.58 %
35.135s : CPU load = 0.59 %
40.135s : CPU load = 0.48 %
Icssg_handleLinkUp:2495
link_callback==UP
status_callback==UP, local interface IP is 192.168.18.125
45.135s : CPU load = 0.63 %
50.135s : CPU load = 1.34 %
55.135s : CPU load = 1.66 %
IPERF report: type=0, remote: 192.168.18.32:10730, total bytes: 1048600, duration in ms: 9200, kbits/s: 904
你好, 上述是我使用 SBL NULL 配置的打印信息,并无明显区别. 下方的iperf测速结果是由于延长定时器触发间隔导致的.在测试过程中, 发现其收发包过程中, 函数Lwip2Enet_rxPacketTask中的 rxPacketSemObj 完全依赖于Lwip2Enet_timerCb进行V操作, 而Lwip2Enet_notifyRxPackets则完全没有被调用, 同时通过打印寄存器, 发现Interrupt Aggregator与GICSS0_SPI对应的寄存器已使能,但并未触发中断
请问您可以分享测试代码吗?工程师想在自己的设备上运行一下以便找出问题
使用 Lwip2Enet_timerCb 而不是 UDMA 中断来接收数据包是因为中断聚合器不支持中断步调(interrupt pacing),如果更改此逻辑,性能则会下降,虽然功能应该不会受到影响。
您好, 我使用的代码是mcu_plus_sdk_am64x_08_04_00_17\examples\networking\lwip\enet_lwip_icssg 路径下的例程, 如果需要测试代码, 最简单的修改方式可以将source\networking\enet\core\lwipif\src\V1\lwip2enet.c路径下的Lwip2Enet_createTimer函数(1474行), 对clkPrms.timeout与clkPrms.period
进行如下改动, 并重新编译, 现象是使用iperf进行测试时, 性能大幅下降.
static void Lwip2Enet_createTimer(Lwip2Enet_Handle hLwip2Enet)
{
ClockP_Params clkPrms;
int32_t status;
ClockP_Params_init(&clkPrms);
clkPrms.start = true;
clkPrms.timeout = 100/* ClockP_usecToTicks(hLwip2Enet->appInfo.timerPeriodUs) */;
clkPrms.period = 100/* ClockP_usecToTicks(hLwip2Enet->appInfo.timerPeriodUs) */;
clkPrms.callback = &Lwip2Enet_timerCb;
clkPrms.args = hLwip2Enet;
status = ClockP_construct(&hLwip2Enet->pacingClkObj, &clkPrms);
Lwip2Enet_assert(status == SystemP_SUCCESS);
}对于 AM64x (UDMA),我们支持 SW 中断中断调步。
但是,我们不支持混合(软件定时器 + 硬件定时器)。
请问您可以访问 bitbucket 吗?工程师可以用硬件中断代码指向分支。
您能否检查并确认以下功能:
- Lwip2Enet_Handle Lwip2Enet_open(struct netif *netif)
有
- EnetDma_disableRxEvent(hLwip2Enet->rx[i].hFlow);
和
- EnetDma_enableRxEvent(hLwip2Enet->rx[i].hFlow);
Tx 也有类似的。
这些 API 用于启用或禁用硬件事件。