K2 Gigabit Ethernet (GbE) Switch Subsystem

typedef struct
{
	CSL_SERDES_REF_CLOCK inputRefClock;

	float linkSpeed_GHz; 	/*the max link speed of all lanes at GHz*/

	/*bit 0~3 control the endable/disable of 4 lanes. 0: disable; 1: enable*/
	Uint32 laneEnableMask; 

	Uint32 internalLoopbackDisableMask;
} K2_GE_SerdesConfig;

char * SerdesErrorStr[]=
{
	"SERDES no error",
	"SERDES error: invalid input reference clock speed!",
	"SERDES error: invalid link speed!"
};
/*Serdes initialization for Giga bit ethernet*/
void K2_GE_Serdes_init(K2_GE_SerdesConfig * serdes_cfg, Uint32 uiBase_addr)
{
	int i;
	CSL_SERDES_LINK_RATE linkSpeed;
	CSL_SERDES_LANE_CTRL_RATE laneRateScale;
	Uint32 uiResult;

	// Disable pll before configuring the SerDes registers
	CSL_EthernetSerdesShutdown(uiBase_addr);

	if(serdes_cfg->linkSpeed_GHz== 1.25f)
	{
		linkSpeed= CSL_SERDES_LINK_RATE_1p25G;
		laneRateScale = CSL_SERDES_LANE_QUARTER_RATE; //???
	}
	else
		printf("Error: link speed %.3fGbps is not supported by SGMII\n",serdes_cfg->linkSpeed_GHz);
	
	uiResult= CSL_EthernetSerdesInit(uiBase_addr,
		serdes_cfg->inputRefClock, linkSpeed);
	if(uiResult)
		printf("  %s\n", SerdesErrorStr[uiResult]);

	for(i=0; i<4; i++)
	{
		if((serdes_cfg->laneEnableMask>>i)&1)
		{
			CSL_EthernetSerdesLaneConfig(uiBase_addr,
				serdes_cfg->inputRefClock, linkSpeed, i);
		}
	}

	CSL_EthernetSerdesComEnable(uiBase_addr);

	for(i=0; i<4; i++)
	{
		if((serdes_cfg->laneEnableMask>>i)&1)
		{
			uiResult= CSL_EthernetSerdesLaneEnable(uiBase_addr,
				i, (serdes_cfg->internalLoopbackDisableMask>>i)&1, laneRateScale);
			if(uiResult)
				printf("  lane %d error: invalid rate scale\n", i);
		}
	}

	// Enable pll via the pll_ctrl 0x0014
	CSL_EthernetSerdesPllEnable(uiBase_addr);

	// Wait the SerDes PLL lock
	while(CSL_SERDES_STATUS_PLL_NOT_LOCKED==K2_SerdesPLLGetStatus(uiBase_addr));
#if 0	
	for(i=0; i<4; i++)
	{
		if(((serdes_cfg->laneEnableMask>>i)&1)&&((serdes_cfg->internalLoopbackDisableMask>>i)&1))
		{
			while(CSL_SERDES_STATUS_PLL_NOT_LOCKED==K2_SerdesLaneGetStatus(uiBase_addr, i));
		}
	}
#endif
}

	 	K2_GE_Serdes_init(&serdes_cfg, CSL_NETCP_SERDES_CFG_REGS);