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请看下面e2e工程师的回复。 This is not specific to AM64x, in general there is no separate DMA involved in a cache miss. The processor core (in AM6442 case A53 or R5) cache controller is the initiator the fetches or evicts a cache line (64bytes with A53, 32bytes with R5) in a burst. You can think of this cache controller as being a dedicated DMA for just the purpose of reading and writing between main memory and caches.
