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加载固件与PCIE的IO内存空间映射问题



我用的PCIE的RC和EP都是DM8168,内存是2G的DDR3。主端在加载PCIE的驱动ti81xx_pcie_bootdrv.ko和ti81xx_pcie_rcdrv.ko后运行load.sh脚本,脚本在加载

dvr_rdk_fw_m3vpss_2048M_512M.xem3时出现“vmap allocation for size 268439552 failed: use vmalloc=<size> to increase size.”错误;

反过来如果先加载M3的固件,后加载PCIE驱动,则PCIE驱动在ioremap他的0x20000000开始的256M地址空间时报通用错误,该如何解决这两部分程序的内存映射?

我的启动参数:bootargs 'mem=512M ddr_mem=2048M console=ttyO0,115200n8 ubi.mtd=4,2048 root=ubi0:rootfs rootwait=1 rootfstype=ubifs rw ip=192.168.1.93:192.168.1.82:192.168.1.1:255.255.255.0::eth0:off vram=50M vmalloc=476M notifyk.vpssm3_sva=0xBFB00000'

  • M3与A8通信的278M的SR1也需重新映射到linux的那段512M内存空间吗?各个核不能直接访问SR1地址空间(0x80000000开始的278M空间)?

    求解啊!

  • 你好,

    请问你的2GB DDR是如何分配的?默认0x80000000开始的地址是Linux的内存,不是SR1.

    你有参考过链接:https://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/341245么?

  • 我用的是RDK4.0,地址是从0xc0000000开始的;之前使用过的RDK3.0的linux内存才是0x80000000开始,我的4.0的版本的内存分配文件 config_2g.bld是这样的:

    var KB=1024; var MB=KB*KB; var GB=KB*KB*KB;

    var DDR3_ADDR                  = 0x80000000;

     var DDR3_SIZE                  = 2048*MB;

    var ETH_OFFLOAD_ADDR           = 0x40300000;

    var ETH_OFFLOAD_SIZE           = 64*KB;

    var OCMC0_ADDR                 = ETH_OFFLOAD_ADDR + ETH_OFFLOAD_SIZE;

     var OCMC1_ADDR                 = 0x40400000;

     var OCMC0_RUN_ADDR             = OCMC0_ADDR - 0x40000000;

     var OCMC1_RUN_ADDR             = OCMC1_ADDR - 0x40000000;

    var OCMC0_SIZE                 = 256*KB - ETH_OFFLOAD_SIZE;

     var OCMC1_SIZE                 = 256*KB;

    var L2_SRAM_ADDR               = 0x55024000; var L2_SRAM_SIZE               = 128*KB;

     var L2_SRAM_RUN_ADDR           = 0x20004000;

    var DUCATI_WB_WA_ADDR          = 0x20000000;

    var TOTAL_MEM_SIZE             = 2048*MB;

    /* FIRST + SECOND 512MB */

     var SR1_SIZE                   = 278 * MB;

     var VIDEO_M3_CODE_SIZE         = 3   * MB;

    var VIDEO_M3_BSS_SIZE          = 15  * MB;

     var VIDEO_M3_DATA_SIZE         = 3   * MB;

     var DSS_M3_CODE_SIZE           = 2   * MB;

    var DSS_M3_BSS_SIZE            = 20  * MB;

     var DSS_M3_DATA_SIZE           = 6   * MB;

    var DSP_CODE_SIZE              = 1   * MB;

     var DSP_DATA_SIZE              = 24  * MB;

    var SR2_FRAME_BUFFER_SIZE      = 640  * MB;

     var VIDEO_M3_EXCEPTION_CTX_SIZE = 128*KB;

    var VPSS_M3_EXCEPTION_CTX_SIZE  = 128*KB;

     var SR0_SIZE                    = 22 * MB + 768 * KB;

     var HDVPSS_DESC_SIZE            = 2  * MB;

     var HDVPSS_SHARED_SIZE          = 2  * MB;

     var NOTIFY_SHARED_SIZE          = 2  * MB;

    var REMOTE_DEBUG_SIZE           = 1  * MB;

    var SHARED_MEMORY_SIZE          = 2  * MB;

    /* THIRD 512MB */

    var TILER_SIZE                  = 256 * MB;

     var SR3_FRAME_BUFFER_EXTRA_SIZE     = 256 * MB;

    /* LAST 512MB */

    var LINUX_SIZE                  = 512 * MB;

    /* first and second 512MB */

     var SR1_ADDR                   = DDR3_ADDR;

    var VIDEO_M3_CODE_ADDR         = SR1_ADDR                        + SR1_SIZE;

     var VIDEO_M3_DATA_ADDR         = VIDEO_M3_CODE_ADDR     + VIDEO_M3_CODE_SIZE;

     var VIDEO_M3_BSS_ADDR          = VIDEO_M3_DATA_ADDR     + VIDEO_M3_DATA_SIZE;

     var VIDEO_M3_BSS_MAPPED_ADDR   = (VIDEO_M3_BSS_ADDR - DDR3_ADDR) + DUCATI_WB_WA_ADDR;

    var DSS_M3_CODE_ADDR           = VIDEO_M3_BSS_ADDR     + VIDEO_M3_BSS_SIZE;

     var DSS_M3_DATA_ADDR           = DSS_M3_CODE_ADDR     + DSS_M3_CODE_SIZE;

     var DSS_M3_BSS_ADDR            = DSS_M3_DATA_ADDR     + DSS_M3_DATA_SIZE;

     var DSS_M3_BSS_MAPPED_ADDR     = (DSS_M3_BSS_ADDR - DDR3_ADDR)  + DUCATI_WB_WA_ADDR;

     var DSP_CODE_ADDR              = DSS_M3_BSS_ADDR     + DSS_M3_BSS_SIZE;

    var DSP_DATA_ADDR              = DSP_CODE_ADDR      + DSP_CODE_SIZE;

     var SR2_FRAME_BUFFER_ADDR      = DSP_DATA_ADDR                    + DSP_DATA_SIZE;

     var VIDEO_M3_EXCEPTION_CTX_ADDR = SR2_FRAME_BUFFER_ADDR         + SR2_FRAME_BUFFER_SIZE;

     var VPSS_M3_EXCEPTION_CTX_ADDR  = VIDEO_M3_EXCEPTION_CTX_ADDR   + VIDEO_M3_EXCEPTION_CTX_SIZE;

    var SR0_ADDR                    = VPSS_M3_EXCEPTION_CTX_ADDR    + VPSS_M3_EXCEPTION_CTX_SIZE;

     var HDVPSS_DESC_ADDR            = SR0_ADDR                      + SR0_SIZE;

     var HDVPSS_SHARED_ADDR          = HDVPSS_DESC_ADDR              + HDVPSS_DESC_SIZE;

    var NOTIFY_SHARED_ADDR          = HDVPSS_SHARED_ADDR            + HDVPSS_SHARED_SIZE;

    var REMOTE_DEBUG_ADDR           = NOTIFY_SHARED_ADDR            + NOTIFY_SHARED_SIZE;

     var SHARED_MEMORY_ADDR          = REMOTE_DEBUG_ADDR             + REMOTE_DEBUG_SIZE;

    var LINUX_ADDR                  = DDR3_ADDR                     + 1 * GB;

    var SR3_FRAME_BUFFER_EXTRA_ADDR = LINUX_ADDR                    + LINUX_SIZE; var TILER_ADDR                  = SR3_FRAME_BUFFER_EXTRA_ADDR   + SR3_FRAME_BUFFER_EXTRA_SIZE;

     

  • 你好,

    从你的bld看,linux的mem是放在0xE0000000起始地址,请问你是使用http://processors.wiki.ti.com/index.php/DM816x_AM389x_PSP_User_Guide#Auto_detection_of_Kernel_Load_Address_and_Run_Time_RAM_Base_Determination这个方法来实现Linux的mem起始地址的修改么?并确认成功了么?

    论坛讨论有人尝试过但失败了,具体见https://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/p/221210/1273409#1273409

  • 我这个配置文件不是我所改的,内存分割应该是和文档DM81xx_DVR_RDK_Memory_Map.pdf里关于2GDDR-512M linux的分配是一致的。我的内核加载地址是:

    Image Name: Linux-2.6.37-2.0.0
    Created: Sun Aug 30 13:06:06 2015
    Image Type: ARM Linux Kernel Image (uncompressed)
    Data Size: 2998172 Bytes = 2927.90 kB = 2.86 MB
    Load Address: c0008000
    Entry Point: c0008000

    下面是那个PDF资料中的内存分配,我感觉应该是按这个配置的,附件是这个配置文件完整内容:

    0x80000000 +--------------------+
    | |
    | 278 MB | (SR1) Bitstream buffer
    {Cached on A8. Cached on M3, although access by DMAs}
    | |
    0x91600000 +--------------------+
    | |
    | 3 MB | Video M3 Code
    | |
    0x91900000 +--------------------+
    | |
    | 15 MB | Video M3 BSS
    | |
    0x92800000 +--------------------+
    | |
    | 3 MB | Video M3 Data
    | |
    0x92B00000 +--------------------+
    | |
    | 2 MB | VPSS M3 Code
    | |
    0x92D00000 +--------------------+
    | |
    | 20 MB | VPSS M3 BSS
    | |
    0x94100000 +--------------------+
    | |
    | 6 MB | VPSS M3 Data
    | |
    0x94700000 +--------------------+
    | |
    | 1 MB | DSP Code
    | |
    0x94800000 +--------------------+
    | |
    | 24 MB | DSP Data
    | |
    0x96000000 +--------------------+
    | |
    | 640 MB | (SR2) Frame Buffer Region
    {VPSS - Video M3 Frame Buf}

    | |
    0xBE000000 +--------------------+
    | |
    | 128 KB | Video M3 exception context
    | |
    0xBE020000 +--------------------+
    | |
    | 128 KB | VPSS M3 exception context
    | |
    0xBE040000 +--------------------+
    | |
    | 22.75 MB | (SR0) Syslink MsgQ/IPC List
    MP - <Non-cached on M3>
    | |
    0xBF700000 +--------------------+
    | |
    | 2 MB | VPSS M3 - VPDMA Descriptor
    | |
    0xBF900000 +--------------------+
    | |
    | 2 MB | VPSS M3 - FBDev Shared Memory
    | |
    0xBFB00000 +--------------------+
    | |
    | 2 MB | Host - VPSS M3 Notify(For
    FBDev)
    | |
    0xBFD00000 +--------------------+
    | |
    | 1 MB | Remote Debug Print
    | |
    0xBFE00000 +--------------------+
    | |
    | 2 MB | Shared Memory application
    inter process communication on A8
    | |

    0xC0000000 +--------------------+
    | |
    | 512 MB | Linux
    | |
    0xE0000000 +--------------------+
    | |
    | 256 MB | SR3_FRAME_BUFFER_EXTRA -
    Extra heap for video frame buffers.Not mapped on M3
    | |
    0xF0000000 +--------------------+
    | |

    | 256 MB | Tiled 8-bit + 16-bit region
    | |
    0xFFFFFFFF +--------------------+