os : RTOS
icssg dirver: porting from uboot in sdk9.0
test method: phy internal loopback
compile chain:
gcc ICSSG1 port0 and port1 work normal
clang + llvm ICSSG1 port0 and port1 sometimes can not receive data.
When powered on, if ICSSG1 port0 and port1 is working properly, the port will work properly.
When powered on, if ICSSG1 port0 and port1 cannot receive data, it cannot receive data all the time
debug method and result :
1、 dump all registers of icssg1 MII_G and CFG , Compare the value of the register under normal and abnormal conditions, the values are the same .
2、 dump the MII_G statics register under abnormal conditions , find that MII_G module have received the data , but The receive interrupt did not occur.