Hi support,
We're doing LPDDR4 layout for AM62D.
After reading this version of the DDR design guide https://www.ti.com/lit/an/sprad66b/sprad66b.pdf, I have several confusions.
1. According to LP4_DRS6 in Table 2-7, the propagation delay of DQSx can be greater than DQ/DM.
However, in 3.5.3.2, 'DQSx delays must be less than the DQ and DM delays in the respective BYTEx' is mentioned. Which design rules should be followed?
2. Besides, is LP4_ACRS3 in Table 2-6 too strict compared to LP4_DRS4 in Table 2-7?
The package delay between DDR0_CK0 and DDR0_CK0_N has exceeded the value LP4_ACRS3. So I want to double confirm.
3. According to LP4_DRS3 in Table 2-7, does CK delay must be greater than DQS?
Thank you
Best regards
Wenjin
