Hello,
I would like to implement PCIe P2P functionality using J721E, with one J721E acting as the RC and the other as the EP.
1.Does J721E(EP mode) support P2P?
2.If the J721E does not support PCIe P2P in EP mode, are there any other product series that can achieve this?
3.I am also unclear about the hardware requirements for enabling PCIe P2P in EP mode. Do you have any related documentation on P2P hardware?
Best regards
Hi,
By P2P, if you mean two EP devices connected to the J721E RC communicating with each other directly with no help from RC, then no PCIe P2P support.
However, the closest to this would be the PCIe backplane Linux demo here in which two RC devices can communicate with each other through a third device that has multiple EP instances: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/10_01_00_04/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/PCIe/PCIe_Backplane.html
Can I get more details on what the full set up is?
For example, is it a SSD EP that the J721E EP is trying to access without interference from J721E RC like below. For this, we do not have support for, and customer will have to write some software similar to the PCIe backplane demo, so that the RC kicks off read/writes to the SSD EP based off of J721E EP's requests.
Regards,
Lydia
Thank you for your reply.
I am aware of the TI NTB solution, but it is not very suitable for my project. Therefore, I am considering the P2P approach.
When you say it is not supported, do you mean that the EP does not support it, or the RC does not support it? I understand that P2P requires support from the RC or a PCIe switch. If the RC does not support it, I can consider using a PCIe switch to implement P2P. However, if the EP itself does not support it, could you explain the reason?
The J721E EP has a DMA controller, correct? Does this mean I can modify the destination address (SSD BAR) in the driver to achieve P2P transfers, assuming the RC supports P2P?
In addition, I cannot see the image you sent.
Best regards.
Hi Ying,
J721E RC does not support since each PCIe port/controller comes up as a separate bridge on J721E.
And he following Linux kernel documentation clarifies the limitations with P2P that makes it tricky to implement:
As for EP not supporting, this will depend on the EP. For example, I have seen FPGA EP that requires very large 64GB mapped to memory space for P2P transactions. J721E limit for PCIe is 4GB space. This is just one example, but you/customer will have to check the EP's datasheet for this one.
And also share some more details on why this feature is needed, and why the backplane example would not work in the customer's usecase?
Regards,
Lydia